stm32g0xx_hal/
dmamux.rs

1use crate::stm32::DMAMUX;
2
3/// Extension trait to split a DMA peripheral into independent channels
4pub trait DmaMuxExt {
5    /// The type to split the DMA into
6    type Channels;
7
8    /// Split the DMA into independent channels
9    fn split(self) -> Self::Channels;
10}
11
12pub enum DmaMuxIndex {
13    dmamux_req_gen0 = 0,
14    dmamux_req_gen1 = 1,
15    dmamux_req_gen2 = 2,
16    dmamux_req_gen3 = 3,
17    ADC = 5,
18
19    #[cfg(any(feature = "stm32g041", feature = "stm32g081"))]
20    AES_IN = 6,
21    #[cfg(any(feature = "stm32g041", feature = "stm32g081"))]
22    AES_OUT = 7,
23    #[cfg(feature = "stm32g0x1")]
24    DAC_Channel1 = 8,
25    #[cfg(feature = "stm32g0x1")]
26    DAC_Channel2 = 9,
27
28    I2C1_RX = 10,
29    I2C1_TX = 11,
30    I2C2_RX = 12,
31    I2C2_TX = 13,
32
33    #[cfg(feature = "stm32g0x1")]
34    LPUART_RX = 14,
35    #[cfg(feature = "stm32g0x1")]
36    LPUART_TX = 15,
37
38    SPI1_RX = 16,
39    SPI1_TX = 17,
40    SPI2_RX = 18,
41    SPI2_TX = 19,
42
43    TIM1_CH1 = 20,
44    TIM1_CH2 = 21,
45    TIM1_CH3 = 22,
46    TIM1_CH4 = 23,
47    TIM1_TRIG_COM = 24,
48    TIM1_UP = 25,
49
50    #[cfg(feature = "stm32g0x1")]
51    TIM2_CH1 = 26,
52    #[cfg(feature = "stm32g0x1")]
53    TIM2_CH2 = 27,
54    #[cfg(feature = "stm32g0x1")]
55    TIM2_CH3 = 28,
56    #[cfg(feature = "stm32g0x1")]
57    TIM2_CH4 = 29,
58    #[cfg(feature = "stm32g0x1")]
59    TIM2_TRIG = 30,
60    #[cfg(feature = "stm32g0x1")]
61    TIM2_UP = 31,
62
63    TIM3_CH1 = 32,
64    TIM3_CH2 = 33,
65    TIM3_CH3 = 34,
66    TIM3_CH4 = 35,
67    TIM3_TRIG = 36,
68    TIM3_UP = 37,
69    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
70    TIM6_UP = 38,
71    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
72    TIM7_UP = 39,
73    TIM15_CH1 = 40,
74    TIM15_CH2 = 41,
75    TIM15_TRIG_COM = 42,
76    TIM15_UP = 43,
77    TIM16_CH1 = 44,
78    TIM16_COM = 45,
79    TIM16_UP = 46,
80    TIM17_CH1 = 47,
81    TIM17_COM = 48,
82    TIM17_UP = 49,
83
84    USART1_RX = 50,
85    USART1_TX = 51,
86    USART2_RX = 52,
87    USART2_TX = 53,
88    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
89    USART3_RX = 54,
90    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
91    USART3_TX = 55,
92    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
93    USART4_RX = 56,
94    #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
95    USART4_TX = 57,
96
97    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
98    UCPD1_RX = 58,
99    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
100    UCPD1_TX = 59,
101    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
102    UCPD2_RX = 60,
103    #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
104    UCPD2_TX = 61,
105}
106
107impl DmaMuxIndex {
108    pub fn val(self) -> u8 {
109        self as u8
110    }
111}
112
113pub enum DmaMuxTriggerSync {
114    EXTI_LINE0 = 0,
115    EXTI_LINE1 = 1,
116    EXTI_LINE2 = 2,
117    EXTI_LINE3 = 3,
118    EXTI_LINE4 = 4,
119    EXTI_LINE5 = 5,
120    EXTI_LINE6 = 6,
121    EXTI_LINE7 = 7,
122    EXTI_LINE8 = 8,
123    EXTI_LINE9 = 9,
124    EXTI_LINE10 = 10,
125    EXTI_LINE11 = 11,
126    EXTI_LINE12 = 12,
127    EXTI_LINE13 = 13,
128    EXTI_LINE14 = 14,
129    EXTI_LINE15 = 15,
130    dmamux_evt0 = 16,
131    dmamux_evt1 = 17,
132    dmamux_evt2 = 18,
133    dmamux_evt3 = 19,
134
135    #[cfg(feature = "stm32g0x1")]
136    LPTIM1_OUT = 20,
137    #[cfg(feature = "stm32g0x1")]
138    LPTIM2_OUT = 21,
139
140    TIM14_OC = 22,
141}
142impl DmaMuxTriggerSync {
143    pub fn val(self) -> u8 {
144        self as u8
145    }
146}
147
148pub trait DmaMuxChannel {
149    fn select_peripheral(&mut self, index: DmaMuxIndex);
150}
151
152macro_rules! dma_mux {
153    (
154        channels: {
155            $( $Ci:ident: ($chi:ident, $cr:ident), )+
156        },
157    ) => {
158
159        /// DMAMUX channels
160        pub struct Channels {
161            $( pub $chi: $Ci, )+
162        }
163
164        $(
165            /// Singleton that represents a DMAMUX channel
166            pub struct $Ci {
167                _0: (),
168            }
169
170            impl DmaMuxChannel for $Ci {
171                fn select_peripheral(&mut self, index: DmaMuxIndex) {
172                    let reg = unsafe { &(*DMAMUX::ptr()).$cr };
173                    reg.write( |w| unsafe {
174                        w.dmareq_id().bits(index.val())
175                        .ege().set_bit()
176                    });
177
178                }
179            }
180        )+
181
182    }
183}
184
185#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
186dma_mux!(
187    channels: {
188        C0: (ch0, dmamux_c0cr),
189        C1: (ch1, dmamux_c1cr),
190        C2: (ch2, dmamux_c2cr),
191        C3: (ch3, dmamux_c3cr),
192        C4: (ch4, dmamux_c4cr),
193        C5: (ch5, dmamux_c5cr),
194        C6: (ch6, dmamux_c6cr),
195    },
196);
197
198#[cfg(any(feature = "stm32g030", feature = "stm32g031", feature = "stm32g041"))]
199dma_mux!(
200    channels: {
201        C0: (ch0, c0cr),
202        C1: (ch1, c1cr),
203        C2: (ch2, c2cr),
204        C3: (ch3, c3cr),
205        C4: (ch4, c4cr),
206    },
207);
208
209impl DmaMuxExt for DMAMUX {
210    type Channels = Channels;
211
212    fn split(self) -> Self::Channels {
213        Channels {
214            ch0: C0 { _0: () },
215            ch1: C1 { _0: () },
216            ch2: C2 { _0: () },
217            ch3: C3 { _0: () },
218            ch4: C4 { _0: () },
219            #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
220            ch5: C5 { _0: () },
221            #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
222            ch6: C6 { _0: () },
223        }
224    }
225}
stm32g0xx_hal/dmamux.rs

stm32g0xx_hal/
dmamux.rs
