Module cfgr1

UCPD configuration register 1

Re-exports

pub use RXORDSETEN0_R as RXORDSETEN1_R;

pub use RXORDSETEN0_R as RXORDSETEN2_R;

pub use RXORDSETEN0_R as RXORDSETEN3_R;

pub use RXORDSETEN0_R as RXORDSETEN4_R;

pub use RXORDSETEN0_R as RXORDSETEN5_R;

pub use RXORDSETEN0_R as RXORDSETEN6_R;

pub use RXORDSETEN0_R as RXORDSETEN7_R;

pub use RXORDSETEN0_R as RXORDSETEN8_R;

pub use RXORDSETEN0_W as RXORDSETEN1_W;

pub use RXORDSETEN0_W as RXORDSETEN2_W;

pub use RXORDSETEN0_W as RXORDSETEN3_W;

pub use RXORDSETEN0_W as RXORDSETEN4_W;

pub use RXORDSETEN0_W as RXORDSETEN5_W;

pub use RXORDSETEN0_W as RXORDSETEN6_W;

pub use RXORDSETEN0_W as RXORDSETEN7_W;

pub use RXORDSETEN0_W as RXORDSETEN8_W;

Structs

CFGR1rs

UCPD configuration register 1

Enums

PSC_USBPDCLK

Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz.

RXDMAEN

Reception DMA mode enable When set, the bit enables DMA mode for reception.

RXORDSETEN0

SOP detection

TXDMAEN

Transmission DMA mode enable When set, the bit enables DMA mode for transmission.

UCPDEN

UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state.

Type Aliases

HBITCLKDIV_R

Field HBITCLKDIV reader - Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a ucpd_clk divider producing half-bit clock (hbit_clk).

HBITCLKDIV_W

Field HBITCLKDIV writer - Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a ucpd_clk divider producing half-bit clock (hbit_clk).

IFRGAP_R

Field IFRGAP reader - Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a ucpd_clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal.

IFRGAP_W

Field IFRGAP writer - Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a ucpd_clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal.

PSC_USBPDCLK_R

Field PSC_USBPDCLK reader - Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz.

PSC_USBPDCLK_W

Field PSC_USBPDCLK writer - Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz.

R

Register CFGR1 reader

RXDMAEN_R

Field RXDMAEN reader - Reception DMA mode enable When set, the bit enables DMA mode for reception.

RXDMAEN_W

Field RXDMAEN writer - Reception DMA mode enable When set, the bit enables DMA mode for reception.

RXORDSETEN0_R

Field RXORDSETEN0 reader - SOP detection

RXORDSETEN0_W

Field RXORDSETEN0 writer - SOP detection

TRANSWIN_R

Field TRANSWIN reader - Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the ucpd_clk frequency and the HBITCLKDIV[5:0] bitfield setting.

TRANSWIN_W

Field TRANSWIN writer - Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the ucpd_clk frequency and the HBITCLKDIV[5:0] bitfield setting.

TXDMAEN_R

Field TXDMAEN reader - Transmission DMA mode enable When set, the bit enables DMA mode for transmission.

TXDMAEN_W

Field TXDMAEN writer - Transmission DMA mode enable When set, the bit enables DMA mode for transmission.

UCPDEN_R

Field UCPDEN reader - UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state.

UCPDEN_W

Field UCPDEN writer - UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state.

W

Register CFGR1 writer