Module stm32g0::stm32g0c1::tim2::ccmr1_output

source · [−]
Expand description

capture/compare mode register 1 (output mode)

Re-exports

pub use OC1M_3_A as OC2M_3_A;
pub use OC1M_3_R as OC2M_3_R;
pub use OC1M_3_W as OC2M_3_W;
pub use OC1M_A as OC2M_A;
pub use OC1M_R as OC2M_R;
pub use OC1M_W as OC2M_W;

Structs

CCMR1_OUTPUT_SPEC

capture/compare mode register 1 (output mode)

R

Register CCMR1_Output reader

W

Register CCMR1_Output writer

Enums

OC1M_3_A

Output Compare 1 mode - bit 3

OC1M_A

Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.

Type Definitions

CC1S_R

Field CC1S reader - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

CC1S_W

Field CC1S writer - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

CC2S_R

Field CC2S reader - Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

CC2S_W

Field CC2S writer - Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).

OC1CE_R

Field OC1CE reader - Output compare 1 clear enable

OC1CE_W

Field OC1CE writer - Output compare 1 clear enable

OC1FE_R

Field OC1FE reader - Output compare 1 fast enable

OC1FE_W

Field OC1FE writer - Output compare 1 fast enable

OC1M_3_R

Field OC1M_3 reader - Output Compare 1 mode - bit 3

OC1M_3_W

Field OC1M_3 writer - Output Compare 1 mode - bit 3

OC1M_R

Field OC1M reader - Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.

OC1M_W

Field OC1M writer - Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.

OC1PE_R

Field OC1PE reader - Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

OC1PE_W

Field OC1PE writer - Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

OC2CE_R

Field OC2CE reader - Output compare 2 clear enable

OC2CE_W

Field OC2CE writer - Output compare 2 clear enable

OC2FE_R

Field OC2FE reader - Output compare 2 fast enable

OC2FE_W

Field OC2FE writer - Output compare 2 fast enable

OC2PE_R

Field OC2PE reader - Output compare 2 preload enable

OC2PE_W

Field OC2PE writer - Output compare 2 preload enable