Module sr

status register

Structs

SRrs

status register

Enums

CC1IFR

Capture/compare %s interrupt flag

CC1IFW

Capture/compare %s interrupt flag

CC1OFR

Capture/Compare %s overcapture flag

CC1OFW

Capture/Compare %s overcapture flag

UIFR

Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=‘0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=‘0’ and UDIS=‘0’ in the TIMx_CR1 register.

UIFW

Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=‘0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=‘0’ and UDIS=‘0’ in the TIMx_CR1 register.

Type Aliases

CCIF_R

Field CCIF(1-1) reader - Capture/compare %s interrupt flag

CCIF_W

Field CCIF(1-1) writer - Capture/compare %s interrupt flag

CCOF_R

Field CCOF(1-1) reader - Capture/Compare %s overcapture flag

CCOF_W

Field CCOF(1-1) writer - Capture/Compare %s overcapture flag

R

Register SR reader

UIF_R

Field UIF reader - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=‘0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=‘0’ and UDIS=‘0’ in the TIMx_CR1 register.

UIF_W

Field UIF writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=‘0’ in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=‘0’ and UDIS=‘0’ in the TIMx_CR1 register.

W

Register SR writer