Expand description
control register 2
Structs
Type Definitions
Field CCDS
reader - Capture/compare DMA selection
Field CCDS
writer - Capture/compare DMA selection
Field CCPC
reader - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
Field CCPC
writer - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
Field CCUS
reader - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
Field CCUS
writer - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
Field MMS2
reader - Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Field MMS2
writer - Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Field MMS
reader - Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Field MMS
writer - Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Field OIS1N
reader - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Field OIS1N
writer - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Field OIS1
reader - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Field OIS1
writer - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Field OIS2N
reader - Output Idle state 2 (OC2N output) Refer to OIS1N bit
Field OIS2N
writer - Output Idle state 2 (OC2N output) Refer to OIS1N bit
Field OIS2
reader - Output Idle state 2 (OC2 output) Refer to OIS1 bit
Field OIS2
writer - Output Idle state 2 (OC2 output) Refer to OIS1 bit
Field OIS3N
reader - Output Idle state 3 (OC3N output) Refer to OIS1N bit
Field OIS3N
writer - Output Idle state 3 (OC3N output) Refer to OIS1N bit
Field OIS3
reader - Output Idle state 3 (OC3 output) Refer to OIS1 bit
Field OIS3
writer - Output Idle state 3 (OC3 output) Refer to OIS1 bit
Field OIS4
reader - Output Idle state 4 (OC4 output) Refer to OIS1 bit
Field OIS4
writer - Output Idle state 4 (OC4 output) Refer to OIS1 bit
Field OIS5
reader - Output Idle state 5 (OC5 output) Refer to OIS1 bit
Field OIS5
writer - Output Idle state 5 (OC5 output) Refer to OIS1 bit
Field OIS6
reader - Output Idle state 6 (OC6 output) Refer to OIS1 bit
Field OIS6
writer - Output Idle state 6 (OC6 output) Refer to OIS1 bit
Field TI1S
reader - TI1 selection
Field TI1S
writer - TI1 selection