Module cr2

SPI control register 2

Structs

CR2rs

SPI control register 2

Enums

DS

Data size These bits configure the data length for SPI transfers. If software attempts to write one of the ‘Not used’ values, they are forced to the value ‘0111’ (8-bit) Note: These bits are not used in I2S mode.

ERRIE

Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).

FRF

Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode.

FRXTH

FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode.

LDMA_RX

Last DMA transfer for reception

LDMA_TX

Last DMA transfer for transmission

NSSP

NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = ‘1’, or FRF = ‘1’. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode.

RXDMAEN

Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.

RXNEIE

RX buffer not empty interrupt enable

SSOE

SS output enable Note: This bit is not used in I2S mode and SPI TI mode.

TXDMAEN

Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.

TXEIE

Tx buffer empty interrupt enable

Type Aliases

DS_R

Field DS reader - Data size These bits configure the data length for SPI transfers. If software attempts to write one of the ‘Not used’ values, they are forced to the value ‘0111’ (8-bit) Note: These bits are not used in I2S mode.

DS_W

Field DS writer - Data size These bits configure the data length for SPI transfers. If software attempts to write one of the ‘Not used’ values, they are forced to the value ‘0111’ (8-bit) Note: These bits are not used in I2S mode.

ERRIE_R

Field ERRIE reader - Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).

ERRIE_W

Field ERRIE writer - Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode).

FRF_R

Field FRF reader - Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode.

FRF_W

Field FRF writer - Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). This bit is not used in I2S mode.

FRXTH_R

Field FRXTH reader - FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode.

FRXTH_W

Field FRXTH writer - FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode.

LDMA_RX_R

Field LDMA_RX reader - Last DMA transfer for reception

LDMA_RX_W

Field LDMA_RX writer - Last DMA transfer for reception

LDMA_TX_R

Field LDMA_TX reader - Last DMA transfer for transmission

LDMA_TX_W

Field LDMA_TX writer - Last DMA transfer for transmission

NSSP_R

Field NSSP reader - NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = ‘1’, or FRF = ‘1’. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode.

NSSP_W

Field NSSP writer - NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = ‘1’, or FRF = ‘1’. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode.

R

Register CR2 reader

RXDMAEN_R

Field RXDMAEN reader - Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.

RXDMAEN_W

Field RXDMAEN writer - Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.

RXNEIE_R

Field RXNEIE reader - RX buffer not empty interrupt enable

RXNEIE_W

Field RXNEIE writer - RX buffer not empty interrupt enable

SSOE_R

Field SSOE reader - SS output enable Note: This bit is not used in I2S mode and SPI TI mode.

SSOE_W

Field SSOE writer - SS output enable Note: This bit is not used in I2S mode and SPI TI mode.

TXDMAEN_R

Field TXDMAEN reader - Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.

TXDMAEN_W

Field TXDMAEN writer - Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.

TXEIE_R

Field TXEIE reader - Tx buffer empty interrupt enable

TXEIE_W

Field TXEIE writer - Tx buffer empty interrupt enable

W

Register CR2 writer