Expand description
Control Register
Structs
Type Definitions
Field CNTSTRT reader - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0]
= ’00â), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0]
different than ’00â), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
Field CNTSTRT writer - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0]
= ’00â), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0]
different than ’00â), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
Field COUNTRST reader - Counter reset This bit is set by software and cleared by hardware. When set to ‘1’ this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to ‘1’ by software before it is already cleared to ‘0’ by hardware. Software should consequently check that COUNTRST bit is already cleared to ‘0’ before attempting to set it to ‘1’.
Field COUNTRST writer - Counter reset This bit is set by software and cleared by hardware. When set to ‘1’ this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to ‘1’ by software before it is already cleared to ‘0’ by hardware. Software should consequently check that COUNTRST bit is already cleared to ‘0’ before attempting to set it to ‘1’.
Field ENABLE reader - LPTIM enable The ENABLE bit is set and cleared by software.
Field ENABLE writer - LPTIM enable The ENABLE bit is set and cleared by software.
Field RSTARE reader - Reset after read enable This bit is set and cleared by software. When RSTARE is set to ‘1’, any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content.
Field RSTARE writer - Reset after read enable This bit is set and cleared by software. When RSTARE is set to ‘1’, any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content.
Field SNGSTRT reader - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0]
= ’00â), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0]
different than ’00â), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
Field SNGSTRT writer - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0]
= ’00â), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0]
different than ’00â), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.