Struct stm32g0::stm32g0b0::tim6::cr1::R

pub struct R(_);

Register CR1 reader

Implementations

impl R

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.

pub fn urs(&self) -> URS_R

Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

Methods from Deref<Target = R<CR1_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CR1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CR1_SPEC>> for R

fn from(reader: R<CR1_SPEC>) -> Self

Converts to this type from the input type.