Type Definition stm32g0::stm32g0b0::tim16::ccmr1_output::OC1M_W

pub type OC1M_W<'a, const O: u8> = FieldWriterSafe<'a, u32, CCMR1_OUTPUT_SPEC, u8, OC1M_A, 3, O>;

Field OC1M writer - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. The OC1M[3] bit is not contiguous, located in bit 16.

Implementations

impl<'a, const O: u8> OC1M_W<'a, O>

pub fn frozen(self) -> &'a mut W

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs

pub fn active_on_match(self) -> &'a mut W

Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register

pub fn inactive_on_match(self) -> &'a mut W

Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register

pub fn toggle(self) -> &'a mut W

OCyREF toggles when TIMx_CNT=TIMx_CCRy

pub fn force_inactive(self) -> &'a mut W

OCyREF is forced low

pub fn force_active(self) -> &'a mut W

OCyREF is forced high

pub fn pwm_mode1(self) -> &'a mut W

In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active

pub fn pwm_mode2(self) -> &'a mut W

Inversely to PwmMode1