Struct stm32g0::stm32g0b0::tim1::sr::R

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pub struct R(_);

Expand description

Register SR reader

Implementations

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impl R

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pub fn uif(&self) -> UIF_R

Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register.

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pub fn cc1if(&self) -> CC1IF_R

Bit 1 - Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).

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pub fn cc2if(&self) -> CC2IF_R

Bit 2 - Capture/Compare 2 interrupt flag Refer to CC1IF description

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pub fn cc3if(&self) -> CC3IF_R

Bit 3 - Capture/Compare 3 interrupt flag Refer to CC1IF description

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pub fn cc4if(&self) -> CC4IF_R

Bit 4 - Capture/Compare 4 interrupt flag Refer to CC1IF description

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pub fn comif(&self) -> COMIF_R

Bit 5 - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software.

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pub fn tif(&self) -> TIF_R

Bit 6 - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.

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pub fn bif(&self) -> BIF_R

Bit 7 - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.

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pub fn b2if(&self) -> B2IF_R

Bit 8 - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active.

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pub fn cc1of(&self) -> CC1OF_R

Bit 9 - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ’0â.

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pub fn cc2of(&self) -> CC2OF_R

Bit 10 - Capture/Compare 2 overcapture flag Refer to CC1OF description

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pub fn cc3of(&self) -> CC3OF_R

Bit 11 - Capture/Compare 3 overcapture flag Refer to CC1OF description

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pub fn cc4of(&self) -> CC4OF_R

Bit 12 - Capture/Compare 4 overcapture flag Refer to CC1OF description

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pub fn sbif(&self) -> SBIF_R

Bit 13 - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation.

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