Module stm32g0::stm32g0b0::tim1::cr2

source · [−]

Expand description

control register 2

Structs

CR2_SPEC

control register 2

R

Register CR2 reader

W

Register CR2 writer

Type Definitions

CCDS_R

Field CCDS reader - Capture/compare DMA selection

CCDS_W

Field CCDS writer - Capture/compare DMA selection

CCPC_R

Field CCPC reader - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.

CCPC_W

Field CCPC writer - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.

CCUS_R

Field CCUS reader - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.

CCUS_W

Field CCUS writer - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.

MMS2_R

Field MMS2 reader - Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

MMS2_W

Field MMS2 writer - Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

MMS_R

Field MMS reader - Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

MMS_W

Field MMS writer - Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

OIS1N_R

Field OIS1N reader - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

OIS1N_W

Field OIS1N writer - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

OIS1_R

Field OIS1 reader - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

OIS1_W

Field OIS1 writer - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

OIS2N_R

Field OIS2N reader - Output Idle state 2 (OC2N output) Refer to OIS1N bit

OIS2N_W

Field OIS2N writer - Output Idle state 2 (OC2N output) Refer to OIS1N bit

OIS2_R

Field OIS2 reader - Output Idle state 2 (OC2 output) Refer to OIS1 bit

OIS2_W

Field OIS2 writer - Output Idle state 2 (OC2 output) Refer to OIS1 bit

OIS3N_R

Field OIS3N reader - Output Idle state 3 (OC3N output) Refer to OIS1N bit

OIS3N_W

Field OIS3N writer - Output Idle state 3 (OC3N output) Refer to OIS1N bit