Module cr2

control register 2

Structs

CR2rs

control register 2

Enums

CCDS

Capture/compare DMA selection

CCPC

Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.

CCUS

Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.

OIS1

Output Idle state (OC%s output)

OIS1N

Output Idle state (OC%sN output)

TI1S

TI1 selection

Type Aliases

CCDS_R

Field CCDS reader - Capture/compare DMA selection

CCDS_W

Field CCDS writer - Capture/compare DMA selection

CCPC_R

Field CCPC reader - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.

CCPC_W

Field CCPC writer - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.

CCUS_R

Field CCUS reader - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.

CCUS_W

Field CCUS writer - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.

MMS2_R

Field MMS2 reader - Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

MMS2_W

Field MMS2 writer - Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

MMS_R

Field MMS reader - Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

MMS_W

Field MMS writer - Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

OISN_R

Field OISN(1-3) reader - Output Idle state (OC%sN output)

OISN_W

Field OISN(1-3) writer - Output Idle state (OC%sN output)

OIS_R

Field OIS(1-6) reader - Output Idle state (OC%s output)

OIS_W

Field OIS(1-6) writer - Output Idle state (OC%s output)

R

Register CR2 reader

TI1S_R

Field TI1S reader - TI1 selection

TI1S_W

Field TI1S writer - TI1 selection

W

Register CR2 writer