Module cr1

Control register 1

Structs

CR1rs

Control register 1

Enums

ADDRIE

Address match Interrupt enable (slave only)

ALERTEN

SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

ANFOFF

Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).

DNF

Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK … Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).

ERRIE

Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)

GCEN

General call enable

NACKIE

Not acknowledge received Interrupt enable

NOSTRETCH

Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).

PE

Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.

PECEN

PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

RXDMAEN

DMA reception requests enable

RXIE

RX Interrupt enable

SBC

Slave byte control This bit is used to enable hardware byte control in slave mode.

SMBDEN

SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

SMBHEN

SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

STOPIE

Stop detection Interrupt enable

TCIE

Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)

TXDMAEN

DMA transmission requests enable

TXIE

TX Interrupt enable

WUPEN

Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . Note: WUPEN can be set only when DNF = ‘0000’

Type Aliases

ADDRIE_R

Field ADDRIE reader - Address match Interrupt enable (slave only)

ADDRIE_W

Field ADDRIE writer - Address match Interrupt enable (slave only)

ALERTEN_R

Field ALERTEN reader - SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

ALERTEN_W

Field ALERTEN writer - SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

ANFOFF_R

Field ANFOFF reader - Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).

ANFOFF_W

Field ANFOFF writer - Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).

DNF_R

Field DNF reader - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK … Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).

DNF_W

Field DNF writer - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK … Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0).

ERRIE_R

Field ERRIE reader - Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)

ERRIE_W

Field ERRIE writer - Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)

GCEN_R

Field GCEN reader - General call enable

GCEN_W

Field GCEN writer - General call enable

NACKIE_R

Field NACKIE reader - Not acknowledge received Interrupt enable

NACKIE_W

Field NACKIE writer - Not acknowledge received Interrupt enable

NOSTRETCH_R

Field NOSTRETCH reader - Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).

NOSTRETCH_W

Field NOSTRETCH writer - Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).

PECEN_R

Field PECEN reader - PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

PECEN_W

Field PECEN writer - PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

PE_R

Field PE reader - Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.

PE_W

Field PE writer - Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.

R

Register CR1 reader

RXDMAEN_R

Field RXDMAEN reader - DMA reception requests enable

RXDMAEN_W

Field RXDMAEN writer - DMA reception requests enable

RXIE_R

Field RXIE reader - RX Interrupt enable

RXIE_W

Field RXIE writer - RX Interrupt enable

SBC_R

Field SBC reader - Slave byte control This bit is used to enable hardware byte control in slave mode.

SBC_W

Field SBC writer - Slave byte control This bit is used to enable hardware byte control in slave mode.

SMBDEN_R

Field SMBDEN reader - SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

SMBDEN_W

Field SMBDEN writer - SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

SMBHEN_R

Field SMBHEN reader - SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

SMBHEN_W

Field SMBHEN writer - SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to .

STOPIE_R

Field STOPIE reader - Stop detection Interrupt enable

STOPIE_W

Field STOPIE writer - Stop detection Interrupt enable

TCIE_R

Field TCIE reader - Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)

TCIE_W

Field TCIE writer - Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)

TXDMAEN_R

Field TXDMAEN reader - DMA transmission requests enable

TXDMAEN_W

Field TXDMAEN writer - DMA transmission requests enable

TXIE_R

Field TXIE reader - TX Interrupt enable

TXIE_W

Field TXIE writer - TX Interrupt enable

W

Register CR1 writer

WUPEN_R

Field WUPEN reader - Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . Note: WUPEN can be set only when DNF = ‘0000’

WUPEN_W

Field WUPEN writer - Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to ‘0’. Refer to . Note: WUPEN can be set only when DNF = ‘0000’