Expand description
Control register 1
Structs
Enums
Address match Interrupt enable (slave only)
SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0]
Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
General call enable
Not acknowledge received Interrupt enable
Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
DMA reception requests enable
RX Interrupt enable
Slave byte control This bit is used to enable hardware byte control in slave mode.
SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Stop detection Interrupt enable
Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
DMA transmission requests enable
TX Interrupt enable
Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to . Note: WUPEN can be set only when DNF = ’0000â
Type Definitions
Field ADDRIE reader - Address match Interrupt enable (slave only)
Field ADDRIE writer - Address match Interrupt enable (slave only)
Field ALERTEN reader - SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field ALERTEN writer - SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field ANFOFF reader - Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Field ANFOFF writer - Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Field DNF reader - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0]
Field DNF writer - Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0]
Field ERRIE reader - Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
Field ERRIE writer - Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)
Field GCEN reader - General call enable
Field GCEN writer - General call enable
Field NACKIE reader - Not acknowledge received Interrupt enable
Field NACKIE writer - Not acknowledge received Interrupt enable
Field NOSTRETCH reader - Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Field NOSTRETCH writer - Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Field PECEN reader - PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field PECEN writer - PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field PE reader - Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
Field PE writer - Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles.
Field RXDMAEN reader - DMA reception requests enable
Field RXDMAEN writer - DMA reception requests enable
Field RXIE reader - RX Interrupt enable
Field RXIE writer - RX Interrupt enable
Field SBC reader - Slave byte control This bit is used to enable hardware byte control in slave mode.
Field SBC writer - Slave byte control This bit is used to enable hardware byte control in slave mode.
Field SMBDEN reader - SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field SMBDEN writer - SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field SMBHEN reader - SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field SMBHEN writer - SMBus Host Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to .
Field STOPIE reader - Stop detection Interrupt enable
Field STOPIE writer - Stop detection Interrupt enable
Field TCIE reader - Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
Field TCIE writer - Transfer Complete interrupt enable Note: Any of these events generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)
Field TXDMAEN reader - DMA transmission requests enable
Field TXDMAEN writer - DMA transmission requests enable
Field TXIE reader - TX Interrupt enable
Field TXIE writer - TX Interrupt enable
Field WUPEN reader - Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to . Note: WUPEN can be set only when DNF = ’0000â
Field WUPEN writer - Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to ’0â. Refer to . Note: WUPEN can be set only when DNF = ’0000â