stm32g0/stm32g0c1/usb/
daddr.rs

1///Register `DADDR` reader
2pub type R = crate::R<DADDRrs>;
3///Register `DADDR` writer
4pub type W = crate::W<DADDRrs>;
5///Field `ADD` reader - Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction
6pub type ADD_R = crate::FieldReader;
7///Field `ADD` writer - Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction
8pub type ADD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9///Field `EF` reader - Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD\[6:0\] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers.
10pub type EF_R = crate::BitReader;
11///Field `EF` writer - Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD\[6:0\] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers.
12pub type EF_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    ///Bits 0:6 - Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction
15    #[inline(always)]
16    pub fn add(&self) -> ADD_R {
17        ADD_R::new((self.bits & 0x7f) as u8)
18    }
19    ///Bit 7 - Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD\[6:0\] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers.
20    #[inline(always)]
21    pub fn ef(&self) -> EF_R {
22        EF_R::new(((self.bits >> 7) & 1) != 0)
23    }
24}
25impl core::fmt::Debug for R {
26    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27        f.debug_struct("DADDR")
28            .field("add", &self.add())
29            .field("ef", &self.ef())
30            .finish()
31    }
32}
33impl W {
34    ///Bits 0:6 - Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction
35    #[inline(always)]
36    pub fn add(&mut self) -> ADD_W<DADDRrs> {
37        ADD_W::new(self, 0)
38    }
39    ///Bit 7 - Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD\[6:0\] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers.
40    #[inline(always)]
41    pub fn ef(&mut self) -> EF_W<DADDRrs> {
42        EF_W::new(self, 7)
43    }
44}
45/**USB device address
46
47You can [`read`](crate::Reg::read) this register and get [`daddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
48
49See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#USB:DADDR)*/
50pub struct DADDRrs;
51impl crate::RegisterSpec for DADDRrs {
52    type Ux = u32;
53}
54///`read()` method returns [`daddr::R`](R) reader structure
55impl crate::Readable for DADDRrs {}
56///`write(|w| ..)` method takes [`daddr::W`](W) writer structure
57impl crate::Writable for DADDRrs {
58    type Safety = crate::Unsafe;
59}
60///`reset()` method sets DADDR to value 0
61impl crate::Resettable for DADDRrs {}
stm32g0/stm32g0c1/usb/daddr.rs

stm32g0/stm32g0c1/usb/
daddr.rs
