stm32g0/stm32g0c1/rcc/
cier.rs

1///Register `CIER` reader
2pub type R = crate::R<CIERrs>;
3///Register `CIER` writer
4pub type W = crate::W<CIERrs>;
5/**LSI ready interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum LSIRDYIE {
11    ///0: Interrupt disabled
12    Disabled = 0,
13    ///1: Interrupt enabled
14    Enabled = 1,
15}
16impl From<LSIRDYIE> for bool {
17    #[inline(always)]
18    fn from(variant: LSIRDYIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `LSIRDYIE` reader - LSI ready interrupt enable
23pub type LSIRDYIE_R = crate::BitReader<LSIRDYIE>;
24impl LSIRDYIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> LSIRDYIE {
28        match self.bits {
29            false => LSIRDYIE::Disabled,
30            true => LSIRDYIE::Enabled,
31        }
32    }
33    ///Interrupt disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == LSIRDYIE::Disabled
37    }
38    ///Interrupt enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == LSIRDYIE::Enabled
42    }
43}
44///Field `LSIRDYIE` writer - LSI ready interrupt enable
45pub type LSIRDYIE_W<'a, REG> = crate::BitWriter<'a, REG, LSIRDYIE>;
46impl<'a, REG> LSIRDYIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(LSIRDYIE::Disabled)
54    }
55    ///Interrupt enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(LSIRDYIE::Enabled)
59    }
60}
61///Field `LSERDYIE` reader - LSE ready interrupt enable
62pub use LSIRDYIE_R as LSERDYIE_R;
63///Field `HSIRDYIE` reader - HSI ready interrupt enable
64pub use LSIRDYIE_R as HSIRDYIE_R;
65///Field `HSERDYIE` reader - HSE ready interrupt enable
66pub use LSIRDYIE_R as HSERDYIE_R;
67///Field `PLLSYSRDYIE` reader - PLL ready interrupt enable
68pub use LSIRDYIE_R as PLLSYSRDYIE_R;
69///Field `LSERDYIE` writer - LSE ready interrupt enable
70pub use LSIRDYIE_W as LSERDYIE_W;
71///Field `HSIRDYIE` writer - HSI ready interrupt enable
72pub use LSIRDYIE_W as HSIRDYIE_W;
73///Field `HSERDYIE` writer - HSE ready interrupt enable
74pub use LSIRDYIE_W as HSERDYIE_W;
75///Field `PLLSYSRDYIE` writer - PLL ready interrupt enable
76pub use LSIRDYIE_W as PLLSYSRDYIE_W;
77impl R {
78    ///Bit 0 - LSI ready interrupt enable
79    #[inline(always)]
80    pub fn lsirdyie(&self) -> LSIRDYIE_R {
81        LSIRDYIE_R::new((self.bits & 1) != 0)
82    }
83    ///Bit 1 - LSE ready interrupt enable
84    #[inline(always)]
85    pub fn lserdyie(&self) -> LSERDYIE_R {
86        LSERDYIE_R::new(((self.bits >> 1) & 1) != 0)
87    }
88    ///Bit 3 - HSI ready interrupt enable
89    #[inline(always)]
90    pub fn hsirdyie(&self) -> HSIRDYIE_R {
91        HSIRDYIE_R::new(((self.bits >> 3) & 1) != 0)
92    }
93    ///Bit 4 - HSE ready interrupt enable
94    #[inline(always)]
95    pub fn hserdyie(&self) -> HSERDYIE_R {
96        HSERDYIE_R::new(((self.bits >> 4) & 1) != 0)
97    }
98    ///Bit 5 - PLL ready interrupt enable
99    #[inline(always)]
100    pub fn pllsysrdyie(&self) -> PLLSYSRDYIE_R {
101        PLLSYSRDYIE_R::new(((self.bits >> 5) & 1) != 0)
102    }
103}
104impl core::fmt::Debug for R {
105    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
106        f.debug_struct("CIER")
107            .field("lsirdyie", &self.lsirdyie())
108            .field("lserdyie", &self.lserdyie())
109            .field("hsirdyie", &self.hsirdyie())
110            .field("hserdyie", &self.hserdyie())
111            .field("pllsysrdyie", &self.pllsysrdyie())
112            .finish()
113    }
114}
115impl W {
116    ///Bit 0 - LSI ready interrupt enable
117    #[inline(always)]
118    pub fn lsirdyie(&mut self) -> LSIRDYIE_W<CIERrs> {
119        LSIRDYIE_W::new(self, 0)
120    }
121    ///Bit 1 - LSE ready interrupt enable
122    #[inline(always)]
123    pub fn lserdyie(&mut self) -> LSERDYIE_W<CIERrs> {
124        LSERDYIE_W::new(self, 1)
125    }
126    ///Bit 3 - HSI ready interrupt enable
127    #[inline(always)]
128    pub fn hsirdyie(&mut self) -> HSIRDYIE_W<CIERrs> {
129        HSIRDYIE_W::new(self, 3)
130    }
131    ///Bit 4 - HSE ready interrupt enable
132    #[inline(always)]
133    pub fn hserdyie(&mut self) -> HSERDYIE_W<CIERrs> {
134        HSERDYIE_W::new(self, 4)
135    }
136    ///Bit 5 - PLL ready interrupt enable
137    #[inline(always)]
138    pub fn pllsysrdyie(&mut self) -> PLLSYSRDYIE_W<CIERrs> {
139        PLLSYSRDYIE_W::new(self, 5)
140    }
141}
142/**Clock interrupt enable register
143
144You can [`read`](crate::Reg::read) this register and get [`cier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
145
146See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CIER)*/
147pub struct CIERrs;
148impl crate::RegisterSpec for CIERrs {
149    type Ux = u32;
150}
151///`read()` method returns [`cier::R`](R) reader structure
152impl crate::Readable for CIERrs {}
153///`write(|w| ..)` method takes [`cier::W`](W) writer structure
154impl crate::Writable for CIERrs {
155    type Safety = crate::Unsafe;
156}
157///`reset()` method sets CIER to value 0
158impl crate::Resettable for CIERrs {}
stm32g0/stm32g0c1/rcc/cier.rs

stm32g0/stm32g0c1/rcc/
cier.rs
