stm32g0/stm32g0c1/fdcan1/cccr.rs
1///Register `CCCR` reader
2pub type R = crate::R<CCCRrs>;
3///Register `CCCR` writer
4pub type W = crate::W<CCCRrs>;
5///Field `INIT` reader - Initialization
6pub type INIT_R = crate::BitReader;
7///Field `INIT` writer - Initialization
8pub type INIT_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `CCE` reader - Configuration change enable
10pub type CCE_R = crate::BitReader;
11///Field `CCE` writer - Configuration change enable
12pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `ASM` reader - ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame. In the optional Restricted Operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time.
14pub type ASM_R = crate::BitReader;
15///Field `ASM` writer - ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame. In the optional Restricted Operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time.
16pub type ASM_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `CSA` reader - Clock stop acknowledge
18pub type CSA_R = crate::BitReader;
19///Field `CSR` reader - Clock stop request
20pub type CSR_R = crate::BitReader;
21///Field `CSR` writer - Clock stop request
22pub type CSR_W<'a, REG> = crate::BitWriter<'a, REG>;
23///Field `MON` reader - Bus monitoring mode Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time.
24pub type MON_R = crate::BitReader;
25///Field `MON` writer - Bus monitoring mode Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time.
26pub type MON_W<'a, REG> = crate::BitWriter<'a, REG>;
27///Field `DAR` reader - Disable automatic retransmission
28pub type DAR_R = crate::BitReader;
29///Field `DAR` writer - Disable automatic retransmission
30pub type DAR_W<'a, REG> = crate::BitWriter<'a, REG>;
31///Field `TEST` reader - Test mode enable
32pub type TEST_R = crate::BitReader;
33///Field `TEST` writer - Test mode enable
34pub type TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
35///Field `FDOE` reader - FD operation enable
36pub type FDOE_R = crate::BitReader;
37///Field `FDOE` writer - FD operation enable
38pub type FDOE_W<'a, REG> = crate::BitWriter<'a, REG>;
39///Field `BRSE` reader - FDCAN bit rate switching
40pub type BRSE_R = crate::BitReader;
41///Field `BRSE` writer - FDCAN bit rate switching
42pub type BRSE_W<'a, REG> = crate::BitWriter<'a, REG>;
43///Field `PXHD` reader - Protocol exception handling disable
44pub type PXHD_R = crate::BitReader;
45///Field `PXHD` writer - Protocol exception handling disable
46pub type PXHD_W<'a, REG> = crate::BitWriter<'a, REG>;
47///Field `EFBI` reader - Edge filtering during bus integration
48pub type EFBI_R = crate::BitReader;
49///Field `EFBI` writer - Edge filtering during bus integration
50pub type EFBI_W<'a, REG> = crate::BitWriter<'a, REG>;
51///Field `TXP` reader - If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame.
52pub type TXP_R = crate::BitReader;
53///Field `TXP` writer - If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame.
54pub type TXP_W<'a, REG> = crate::BitWriter<'a, REG>;
55///Field `NISO` reader - Non ISO operation If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
56pub type NISO_R = crate::BitReader;
57///Field `NISO` writer - Non ISO operation If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
58pub type NISO_W<'a, REG> = crate::BitWriter<'a, REG>;
59impl R {
60 ///Bit 0 - Initialization
61 #[inline(always)]
62 pub fn init(&self) -> INIT_R {
63 INIT_R::new((self.bits & 1) != 0)
64 }
65 ///Bit 1 - Configuration change enable
66 #[inline(always)]
67 pub fn cce(&self) -> CCE_R {
68 CCE_R::new(((self.bits >> 1) & 1) != 0)
69 }
70 ///Bit 2 - ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame. In the optional Restricted Operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time.
71 #[inline(always)]
72 pub fn asm(&self) -> ASM_R {
73 ASM_R::new(((self.bits >> 2) & 1) != 0)
74 }
75 ///Bit 3 - Clock stop acknowledge
76 #[inline(always)]
77 pub fn csa(&self) -> CSA_R {
78 CSA_R::new(((self.bits >> 3) & 1) != 0)
79 }
80 ///Bit 4 - Clock stop request
81 #[inline(always)]
82 pub fn csr(&self) -> CSR_R {
83 CSR_R::new(((self.bits >> 4) & 1) != 0)
84 }
85 ///Bit 5 - Bus monitoring mode Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time.
86 #[inline(always)]
87 pub fn mon(&self) -> MON_R {
88 MON_R::new(((self.bits >> 5) & 1) != 0)
89 }
90 ///Bit 6 - Disable automatic retransmission
91 #[inline(always)]
92 pub fn dar(&self) -> DAR_R {
93 DAR_R::new(((self.bits >> 6) & 1) != 0)
94 }
95 ///Bit 7 - Test mode enable
96 #[inline(always)]
97 pub fn test(&self) -> TEST_R {
98 TEST_R::new(((self.bits >> 7) & 1) != 0)
99 }
100 ///Bit 8 - FD operation enable
101 #[inline(always)]
102 pub fn fdoe(&self) -> FDOE_R {
103 FDOE_R::new(((self.bits >> 8) & 1) != 0)
104 }
105 ///Bit 9 - FDCAN bit rate switching
106 #[inline(always)]
107 pub fn brse(&self) -> BRSE_R {
108 BRSE_R::new(((self.bits >> 9) & 1) != 0)
109 }
110 ///Bit 12 - Protocol exception handling disable
111 #[inline(always)]
112 pub fn pxhd(&self) -> PXHD_R {
113 PXHD_R::new(((self.bits >> 12) & 1) != 0)
114 }
115 ///Bit 13 - Edge filtering during bus integration
116 #[inline(always)]
117 pub fn efbi(&self) -> EFBI_R {
118 EFBI_R::new(((self.bits >> 13) & 1) != 0)
119 }
120 ///Bit 14 - If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame.
121 #[inline(always)]
122 pub fn txp(&self) -> TXP_R {
123 TXP_R::new(((self.bits >> 14) & 1) != 0)
124 }
125 ///Bit 15 - Non ISO operation If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
126 #[inline(always)]
127 pub fn niso(&self) -> NISO_R {
128 NISO_R::new(((self.bits >> 15) & 1) != 0)
129 }
130}
131impl core::fmt::Debug for R {
132 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
133 f.debug_struct("CCCR")
134 .field("init", &self.init())
135 .field("cce", &self.cce())
136 .field("asm", &self.asm())
137 .field("csa", &self.csa())
138 .field("csr", &self.csr())
139 .field("mon", &self.mon())
140 .field("dar", &self.dar())
141 .field("test", &self.test())
142 .field("fdoe", &self.fdoe())
143 .field("brse", &self.brse())
144 .field("pxhd", &self.pxhd())
145 .field("efbi", &self.efbi())
146 .field("txp", &self.txp())
147 .field("niso", &self.niso())
148 .finish()
149 }
150}
151impl W {
152 ///Bit 0 - Initialization
153 #[inline(always)]
154 pub fn init(&mut self) -> INIT_W<CCCRrs> {
155 INIT_W::new(self, 0)
156 }
157 ///Bit 1 - Configuration change enable
158 #[inline(always)]
159 pub fn cce(&mut self) -> CCE_W<CCCRrs> {
160 CCE_W::new(self, 1)
161 }
162 ///Bit 2 - ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame. In the optional Restricted Operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time.
163 #[inline(always)]
164 pub fn asm(&mut self) -> ASM_W<CCCRrs> {
165 ASM_W::new(self, 2)
166 }
167 ///Bit 4 - Clock stop request
168 #[inline(always)]
169 pub fn csr(&mut self) -> CSR_W<CCCRrs> {
170 CSR_W::new(self, 4)
171 }
172 ///Bit 5 - Bus monitoring mode Bit MON can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the Host at any time.
173 #[inline(always)]
174 pub fn mon(&mut self) -> MON_W<CCCRrs> {
175 MON_W::new(self, 5)
176 }
177 ///Bit 6 - Disable automatic retransmission
178 #[inline(always)]
179 pub fn dar(&mut self) -> DAR_W<CCCRrs> {
180 DAR_W::new(self, 6)
181 }
182 ///Bit 7 - Test mode enable
183 #[inline(always)]
184 pub fn test(&mut self) -> TEST_W<CCCRrs> {
185 TEST_W::new(self, 7)
186 }
187 ///Bit 8 - FD operation enable
188 #[inline(always)]
189 pub fn fdoe(&mut self) -> FDOE_W<CCCRrs> {
190 FDOE_W::new(self, 8)
191 }
192 ///Bit 9 - FDCAN bit rate switching
193 #[inline(always)]
194 pub fn brse(&mut self) -> BRSE_W<CCCRrs> {
195 BRSE_W::new(self, 9)
196 }
197 ///Bit 12 - Protocol exception handling disable
198 #[inline(always)]
199 pub fn pxhd(&mut self) -> PXHD_W<CCCRrs> {
200 PXHD_W::new(self, 12)
201 }
202 ///Bit 13 - Edge filtering during bus integration
203 #[inline(always)]
204 pub fn efbi(&mut self) -> EFBI_W<CCCRrs> {
205 EFBI_W::new(self, 13)
206 }
207 ///Bit 14 - If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame.
208 #[inline(always)]
209 pub fn txp(&mut self) -> TXP_W<CCCRrs> {
210 TXP_W::new(self, 14)
211 }
212 ///Bit 15 - Non ISO operation If this bit is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
213 #[inline(always)]
214 pub fn niso(&mut self) -> NISO_W<CCCRrs> {
215 NISO_W::new(self, 15)
216 }
217}
218/**FDCAN CC control register
219
220You can [`read`](crate::Reg::read) this register and get [`cccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
221
222See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#FDCAN1:CCCR)*/
223pub struct CCCRrs;
224impl crate::RegisterSpec for CCCRrs {
225 type Ux = u32;
226}
227///`read()` method returns [`cccr::R`](R) reader structure
228impl crate::Readable for CCCRrs {}
229///`write(|w| ..)` method takes [`cccr::W`](W) writer structure
230impl crate::Writable for CCCRrs {
231 type Safety = crate::Unsafe;
232}
233///`reset()` method sets CCCR to value 0x01
234impl crate::Resettable for CCCRrs {
235 const RESET_VALUE: u32 = 0x01;
236}