stm32g0/stm32g0c1/
exti.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    rtsr1: RTSR1,
6    ftsr1: FTSR1,
7    swier1: SWIER1,
8    rpr1: RPR1,
9    fpr1: FPR1,
10    _reserved5: [u8; 0x14],
11    rtsr2: RTSR2,
12    ftsr2: FTSR2,
13    swier2: SWIER2,
14    rpr2: RPR2,
15    fpr2: FPR2,
16    _reserved10: [u8; 0x24],
17    exticr1: EXTICR1,
18    exticr2: EXTICR2,
19    exticr3: EXTICR3,
20    exticr4: EXTICR4,
21    _reserved14: [u8; 0x10],
22    imr1: IMR1,
23    emr1: EMR1,
24    _reserved16: [u8; 0x08],
25    imr2: IMR2,
26    emr2: EMR2,
27}
28impl RegisterBlock {
29    ///0x00 - EXTI rising trigger selection register
30    #[inline(always)]
31    pub const fn rtsr1(&self) -> &RTSR1 {
32        &self.rtsr1
33    }
34    ///0x04 - EXTI falling trigger selection register
35    #[inline(always)]
36    pub const fn ftsr1(&self) -> &FTSR1 {
37        &self.ftsr1
38    }
39    ///0x08 - EXTI software interrupt event register
40    #[inline(always)]
41    pub const fn swier1(&self) -> &SWIER1 {
42        &self.swier1
43    }
44    ///0x0c - EXTI rising edge pending register
45    #[inline(always)]
46    pub const fn rpr1(&self) -> &RPR1 {
47        &self.rpr1
48    }
49    ///0x10 - EXTI falling edge pending register
50    #[inline(always)]
51    pub const fn fpr1(&self) -> &FPR1 {
52        &self.fpr1
53    }
54    ///0x28 - EXTI rising trigger selection register 2
55    #[inline(always)]
56    pub const fn rtsr2(&self) -> &RTSR2 {
57        &self.rtsr2
58    }
59    ///0x2c - EXTI falling trigger selection register 2
60    #[inline(always)]
61    pub const fn ftsr2(&self) -> &FTSR2 {
62        &self.ftsr2
63    }
64    ///0x30 - EXTI software interrupt event register 2
65    #[inline(always)]
66    pub const fn swier2(&self) -> &SWIER2 {
67        &self.swier2
68    }
69    ///0x34 - EXTI rising edge pending register 2
70    #[inline(always)]
71    pub const fn rpr2(&self) -> &RPR2 {
72        &self.rpr2
73    }
74    ///0x38 - EXTI falling edge pending register 2
75    #[inline(always)]
76    pub const fn fpr2(&self) -> &FPR2 {
77        &self.fpr2
78    }
79    ///0x60 - EXTI external interrupt selection register
80    #[inline(always)]
81    pub const fn exticr1(&self) -> &EXTICR1 {
82        &self.exticr1
83    }
84    ///0x64 - EXTI external interrupt selection register
85    #[inline(always)]
86    pub const fn exticr2(&self) -> &EXTICR2 {
87        &self.exticr2
88    }
89    ///0x68 - EXTI external interrupt selection register
90    #[inline(always)]
91    pub const fn exticr3(&self) -> &EXTICR3 {
92        &self.exticr3
93    }
94    ///0x6c - EXTI external interrupt selection register
95    #[inline(always)]
96    pub const fn exticr4(&self) -> &EXTICR4 {
97        &self.exticr4
98    }
99    ///0x80 - EXTI CPU wakeup with interrupt mask register
100    #[inline(always)]
101    pub const fn imr1(&self) -> &IMR1 {
102        &self.imr1
103    }
104    ///0x84 - EXTI CPU wakeup with event mask register
105    #[inline(always)]
106    pub const fn emr1(&self) -> &EMR1 {
107        &self.emr1
108    }
109    ///0x90 - EXTI CPU wakeup with interrupt mask register
110    #[inline(always)]
111    pub const fn imr2(&self) -> &IMR2 {
112        &self.imr2
113    }
114    ///0x94 - EXTI CPU wakeup with event mask register
115    #[inline(always)]
116    pub const fn emr2(&self) -> &EMR2 {
117        &self.emr2
118    }
119}
120/**RTSR1 (rw) register accessor: EXTI rising trigger selection register
121
122You can [`read`](crate::Reg::read) this register and get [`rtsr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtsr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:RTSR1)
125
126For information about available fields see [`mod@rtsr1`] module*/
127pub type RTSR1 = crate::Reg<rtsr1::RTSR1rs>;
128///EXTI rising trigger selection register
129pub mod rtsr1;
130/**FTSR1 (rw) register accessor: EXTI falling trigger selection register
131
132You can [`read`](crate::Reg::read) this register and get [`ftsr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ftsr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:FTSR1)
135
136For information about available fields see [`mod@ftsr1`] module*/
137pub type FTSR1 = crate::Reg<ftsr1::FTSR1rs>;
138///EXTI falling trigger selection register
139pub mod ftsr1;
140/**SWIER1 (rw) register accessor: EXTI software interrupt event register
141
142You can [`read`](crate::Reg::read) this register and get [`swier1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swier1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:SWIER1)
145
146For information about available fields see [`mod@swier1`] module*/
147pub type SWIER1 = crate::Reg<swier1::SWIER1rs>;
148///EXTI software interrupt event register
149pub mod swier1;
150/**RPR1 (rw) register accessor: EXTI rising edge pending register
151
152You can [`read`](crate::Reg::read) this register and get [`rpr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:RPR1)
155
156For information about available fields see [`mod@rpr1`] module*/
157pub type RPR1 = crate::Reg<rpr1::RPR1rs>;
158///EXTI rising edge pending register
159pub mod rpr1;
160/**FPR1 (rw) register accessor: EXTI falling edge pending register
161
162You can [`read`](crate::Reg::read) this register and get [`fpr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
163
164See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:FPR1)
165
166For information about available fields see [`mod@fpr1`] module*/
167pub type FPR1 = crate::Reg<fpr1::FPR1rs>;
168///EXTI falling edge pending register
169pub mod fpr1;
170/**RTSR2 (rw) register accessor: EXTI rising trigger selection register 2
171
172You can [`read`](crate::Reg::read) this register and get [`rtsr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtsr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
173
174See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:RTSR2)
175
176For information about available fields see [`mod@rtsr2`] module*/
177pub type RTSR2 = crate::Reg<rtsr2::RTSR2rs>;
178///EXTI rising trigger selection register 2
179pub mod rtsr2;
180/**FTSR2 (rw) register accessor: EXTI falling trigger selection register 2
181
182You can [`read`](crate::Reg::read) this register and get [`ftsr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ftsr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:FTSR2)
185
186For information about available fields see [`mod@ftsr2`] module*/
187pub type FTSR2 = crate::Reg<ftsr2::FTSR2rs>;
188///EXTI falling trigger selection register 2
189pub mod ftsr2;
190/**SWIER2 (rw) register accessor: EXTI software interrupt event register 2
191
192You can [`read`](crate::Reg::read) this register and get [`swier2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swier2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
193
194See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:SWIER2)
195
196For information about available fields see [`mod@swier2`] module*/
197pub type SWIER2 = crate::Reg<swier2::SWIER2rs>;
198///EXTI software interrupt event register 2
199pub mod swier2;
200/**RPR2 (rw) register accessor: EXTI rising edge pending register 2
201
202You can [`read`](crate::Reg::read) this register and get [`rpr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
203
204See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:RPR2)
205
206For information about available fields see [`mod@rpr2`] module*/
207pub type RPR2 = crate::Reg<rpr2::RPR2rs>;
208///EXTI rising edge pending register 2
209pub mod rpr2;
210/**FPR2 (rw) register accessor: EXTI falling edge pending register 2
211
212You can [`read`](crate::Reg::read) this register and get [`fpr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:FPR2)
215
216For information about available fields see [`mod@fpr2`] module*/
217pub type FPR2 = crate::Reg<fpr2::FPR2rs>;
218///EXTI falling edge pending register 2
219pub mod fpr2;
220/**EXTICR1 (rw) register accessor: EXTI external interrupt selection register
221
222You can [`read`](crate::Reg::read) this register and get [`exticr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
223
224See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:EXTICR1)
225
226For information about available fields see [`mod@exticr1`] module*/
227pub type EXTICR1 = crate::Reg<exticr1::EXTICR1rs>;
228///EXTI external interrupt selection register
229pub mod exticr1;
230/**EXTICR2 (rw) register accessor: EXTI external interrupt selection register
231
232You can [`read`](crate::Reg::read) this register and get [`exticr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
233
234See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:EXTICR2)
235
236For information about available fields see [`mod@exticr2`] module*/
237pub type EXTICR2 = crate::Reg<exticr2::EXTICR2rs>;
238///EXTI external interrupt selection register
239pub mod exticr2;
240/**EXTICR3 (rw) register accessor: EXTI external interrupt selection register
241
242You can [`read`](crate::Reg::read) this register and get [`exticr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
243
244See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:EXTICR3)
245
246For information about available fields see [`mod@exticr3`] module*/
247pub type EXTICR3 = crate::Reg<exticr3::EXTICR3rs>;
248///EXTI external interrupt selection register
249pub mod exticr3;
250/**EXTICR4 (rw) register accessor: EXTI external interrupt selection register
251
252You can [`read`](crate::Reg::read) this register and get [`exticr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
253
254See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:EXTICR4)
255
256For information about available fields see [`mod@exticr4`] module*/
257pub type EXTICR4 = crate::Reg<exticr4::EXTICR4rs>;
258///EXTI external interrupt selection register
259pub mod exticr4;
260/**IMR1 (rw) register accessor: EXTI CPU wakeup with interrupt mask register
261
262You can [`read`](crate::Reg::read) this register and get [`imr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
263
264See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:IMR1)
265
266For information about available fields see [`mod@imr1`] module*/
267pub type IMR1 = crate::Reg<imr1::IMR1rs>;
268///EXTI CPU wakeup with interrupt mask register
269pub mod imr1;
270/**EMR1 (rw) register accessor: EXTI CPU wakeup with event mask register
271
272You can [`read`](crate::Reg::read) this register and get [`emr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
273
274See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:EMR1)
275
276For information about available fields see [`mod@emr1`] module*/
277pub type EMR1 = crate::Reg<emr1::EMR1rs>;
278///EXTI CPU wakeup with event mask register
279pub mod emr1;
280/**IMR2 (rw) register accessor: EXTI CPU wakeup with interrupt mask register
281
282You can [`read`](crate::Reg::read) this register and get [`imr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
283
284See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:IMR2)
285
286For information about available fields see [`mod@imr2`] module*/
287pub type IMR2 = crate::Reg<imr2::IMR2rs>;
288///EXTI CPU wakeup with interrupt mask register
289pub mod imr2;
290/**EMR2 (rw) register accessor: EXTI CPU wakeup with event mask register
291
292You can [`read`](crate::Reg::read) this register and get [`emr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
293
294See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#EXTI:EMR2)
295
296For information about available fields see [`mod@emr2`] module*/
297pub type EMR2 = crate::Reg<emr2::EMR2rs>;
298///EXTI CPU wakeup with event mask register
299pub mod emr2;
stm32g0/stm32g0c1/exti.rs

stm32g0/stm32g0c1/
exti.rs
