stm32g0/stm32g0c1/adc/
isr.rs

1///Register `ISR` reader
2pub type R = crate::R<ISRrs>;
3///Register `ISR` writer
4pub type W = crate::W<ISRrs>;
5/**ADC ready This bit is set by hardware after the ADC has been enabled (ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ADRDYR {
11    ///0: ADC not yet ready to start conversion
12    NotReady = 0,
13    ///1: ADC ready to start conversion
14    Ready = 1,
15}
16impl From<ADRDYR> for bool {
17    #[inline(always)]
18    fn from(variant: ADRDYR) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ADRDY` reader - ADC ready This bit is set by hardware after the ADC has been enabled (ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
23pub type ADRDY_R = crate::BitReader<ADRDYR>;
24impl ADRDY_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ADRDYR {
28        match self.bits {
29            false => ADRDYR::NotReady,
30            true => ADRDYR::Ready,
31        }
32    }
33    ///ADC not yet ready to start conversion
34    #[inline(always)]
35    pub fn is_not_ready(&self) -> bool {
36        *self == ADRDYR::NotReady
37    }
38    ///ADC ready to start conversion
39    #[inline(always)]
40    pub fn is_ready(&self) -> bool {
41        *self == ADRDYR::Ready
42    }
43}
44/**ADC ready This bit is set by hardware after the ADC has been enabled (ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum ADRDYW {
50    ///1: Clear the ADC ready flag
51    Clear = 1,
52}
53impl From<ADRDYW> for bool {
54    #[inline(always)]
55    fn from(variant: ADRDYW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `ADRDY` writer - ADC ready This bit is set by hardware after the ADC has been enabled (ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
60pub type ADRDY_W<'a, REG> = crate::BitWriter1C<'a, REG, ADRDYW>;
61impl<'a, REG> ADRDY_W<'a, REG>
62where
63    REG: crate::Writable + crate::RegisterSpec,
64{
65    ///Clear the ADC ready flag
66    #[inline(always)]
67    pub fn clear(self) -> &'a mut crate::W<REG> {
68        self.variant(ADRDYW::Clear)
69    }
70}
71/**End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1'.
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum EOSMPR {
77    ///0: Not at the end of the samplings phase
78    NotAtEnd = 0,
79    ///1: End of sampling phase reached
80    AtEnd = 1,
81}
82impl From<EOSMPR> for bool {
83    #[inline(always)]
84    fn from(variant: EOSMPR) -> Self {
85        variant as u8 != 0
86    }
87}
88///Field `EOSMP` reader - End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1'.
89pub type EOSMP_R = crate::BitReader<EOSMPR>;
90impl EOSMP_R {
91    ///Get enumerated values variant
92    #[inline(always)]
93    pub const fn variant(&self) -> EOSMPR {
94        match self.bits {
95            false => EOSMPR::NotAtEnd,
96            true => EOSMPR::AtEnd,
97        }
98    }
99    ///Not at the end of the samplings phase
100    #[inline(always)]
101    pub fn is_not_at_end(&self) -> bool {
102        *self == EOSMPR::NotAtEnd
103    }
104    ///End of sampling phase reached
105    #[inline(always)]
106    pub fn is_at_end(&self) -> bool {
107        *self == EOSMPR::AtEnd
108    }
109}
110/**End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1'.
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum EOSMPW {
116    ///1: Clear the sampling phase flag
117    Clear = 1,
118}
119impl From<EOSMPW> for bool {
120    #[inline(always)]
121    fn from(variant: EOSMPW) -> Self {
122        variant as u8 != 0
123    }
124}
125///Field `EOSMP` writer - End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1'.
126pub type EOSMP_W<'a, REG> = crate::BitWriter1C<'a, REG, EOSMPW>;
127impl<'a, REG> EOSMP_W<'a, REG>
128where
129    REG: crate::Writable + crate::RegisterSpec,
130{
131    ///Clear the sampling phase flag
132    #[inline(always)]
133    pub fn clear(self) -> &'a mut crate::W<REG> {
134        self.variant(EOSMPW::Clear)
135    }
136}
137/**End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum EOCR {
143    ///0: Channel conversion is not complete
144    NotComplete = 0,
145    ///1: Channel conversion complete
146    Complete = 1,
147}
148impl From<EOCR> for bool {
149    #[inline(always)]
150    fn from(variant: EOCR) -> Self {
151        variant as u8 != 0
152    }
153}
154///Field `EOC` reader - End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
155pub type EOC_R = crate::BitReader<EOCR>;
156impl EOC_R {
157    ///Get enumerated values variant
158    #[inline(always)]
159    pub const fn variant(&self) -> EOCR {
160        match self.bits {
161            false => EOCR::NotComplete,
162            true => EOCR::Complete,
163        }
164    }
165    ///Channel conversion is not complete
166    #[inline(always)]
167    pub fn is_not_complete(&self) -> bool {
168        *self == EOCR::NotComplete
169    }
170    ///Channel conversion complete
171    #[inline(always)]
172    pub fn is_complete(&self) -> bool {
173        *self == EOCR::Complete
174    }
175}
176/**End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum EOCW {
182    ///1: Clear the channel conversion flag
183    Clear = 1,
184}
185impl From<EOCW> for bool {
186    #[inline(always)]
187    fn from(variant: EOCW) -> Self {
188        variant as u8 != 0
189    }
190}
191///Field `EOC` writer - End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
192pub type EOC_W<'a, REG> = crate::BitWriter1C<'a, REG, EOCW>;
193impl<'a, REG> EOC_W<'a, REG>
194where
195    REG: crate::Writable + crate::RegisterSpec,
196{
197    ///Clear the channel conversion flag
198    #[inline(always)]
199    pub fn clear(self) -> &'a mut crate::W<REG> {
200        self.variant(EOCW::Clear)
201    }
202}
203/**End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
204
205Value on reset: 0*/
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum EOSR {
209    ///0: Conversion sequence is not complete
210    NotComplete = 0,
211    ///1: Conversion sequence complete
212    Complete = 1,
213}
214impl From<EOSR> for bool {
215    #[inline(always)]
216    fn from(variant: EOSR) -> Self {
217        variant as u8 != 0
218    }
219}
220///Field `EOS` reader - End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
221pub type EOS_R = crate::BitReader<EOSR>;
222impl EOS_R {
223    ///Get enumerated values variant
224    #[inline(always)]
225    pub const fn variant(&self) -> EOSR {
226        match self.bits {
227            false => EOSR::NotComplete,
228            true => EOSR::Complete,
229        }
230    }
231    ///Conversion sequence is not complete
232    #[inline(always)]
233    pub fn is_not_complete(&self) -> bool {
234        *self == EOSR::NotComplete
235    }
236    ///Conversion sequence complete
237    #[inline(always)]
238    pub fn is_complete(&self) -> bool {
239        *self == EOSR::Complete
240    }
241}
242/**End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
243
244Value on reset: 0*/
245#[cfg_attr(feature = "defmt", derive(defmt::Format))]
246#[derive(Clone, Copy, Debug, PartialEq, Eq)]
247pub enum EOSW {
248    ///1: Clear the conversion sequence flag
249    Clear = 1,
250}
251impl From<EOSW> for bool {
252    #[inline(always)]
253    fn from(variant: EOSW) -> Self {
254        variant as u8 != 0
255    }
256}
257///Field `EOS` writer - End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
258pub type EOS_W<'a, REG> = crate::BitWriter1C<'a, REG, EOSW>;
259impl<'a, REG> EOS_W<'a, REG>
260where
261    REG: crate::Writable + crate::RegisterSpec,
262{
263    ///Clear the conversion sequence flag
264    #[inline(always)]
265    pub fn clear(self) -> &'a mut crate::W<REG> {
266        self.variant(EOSW::Clear)
267    }
268}
269/**ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
270
271Value on reset: 0*/
272#[cfg_attr(feature = "defmt", derive(defmt::Format))]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum OVRR {
275    ///0: No overrun occurred
276    NoOverrun = 0,
277    ///1: Overrun occurred
278    Overrun = 1,
279}
280impl From<OVRR> for bool {
281    #[inline(always)]
282    fn from(variant: OVRR) -> Self {
283        variant as u8 != 0
284    }
285}
286///Field `OVR` reader - ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
287pub type OVR_R = crate::BitReader<OVRR>;
288impl OVR_R {
289    ///Get enumerated values variant
290    #[inline(always)]
291    pub const fn variant(&self) -> OVRR {
292        match self.bits {
293            false => OVRR::NoOverrun,
294            true => OVRR::Overrun,
295        }
296    }
297    ///No overrun occurred
298    #[inline(always)]
299    pub fn is_no_overrun(&self) -> bool {
300        *self == OVRR::NoOverrun
301    }
302    ///Overrun occurred
303    #[inline(always)]
304    pub fn is_overrun(&self) -> bool {
305        *self == OVRR::Overrun
306    }
307}
308/**ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
309
310Value on reset: 0*/
311#[cfg_attr(feature = "defmt", derive(defmt::Format))]
312#[derive(Clone, Copy, Debug, PartialEq, Eq)]
313pub enum OVRW {
314    ///1: Clear the overrun flag
315    Clear = 1,
316}
317impl From<OVRW> for bool {
318    #[inline(always)]
319    fn from(variant: OVRW) -> Self {
320        variant as u8 != 0
321    }
322}
323///Field `OVR` writer - ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
324pub type OVR_W<'a, REG> = crate::BitWriter1C<'a, REG, OVRW>;
325impl<'a, REG> OVR_W<'a, REG>
326where
327    REG: crate::Writable + crate::RegisterSpec,
328{
329    ///Clear the overrun flag
330    #[inline(always)]
331    pub fn clear(self) -> &'a mut crate::W<REG> {
332        self.variant(OVRW::Clear)
333    }
334}
335/**Analog watchdog %s flag
336
337Value on reset: 0*/
338#[cfg_attr(feature = "defmt", derive(defmt::Format))]
339#[derive(Clone, Copy, Debug, PartialEq, Eq)]
340pub enum AWD1R {
341    ///0: No analog watchdog event occurred
342    NoEvent = 0,
343    ///1: Analog watchdog event occurred
344    Event = 1,
345}
346impl From<AWD1R> for bool {
347    #[inline(always)]
348    fn from(variant: AWD1R) -> Self {
349        variant as u8 != 0
350    }
351}
352///Field `AWD(1-3)` reader - Analog watchdog %s flag
353pub type AWD_R = crate::BitReader<AWD1R>;
354impl AWD_R {
355    ///Get enumerated values variant
356    #[inline(always)]
357    pub const fn variant(&self) -> AWD1R {
358        match self.bits {
359            false => AWD1R::NoEvent,
360            true => AWD1R::Event,
361        }
362    }
363    ///No analog watchdog event occurred
364    #[inline(always)]
365    pub fn is_no_event(&self) -> bool {
366        *self == AWD1R::NoEvent
367    }
368    ///Analog watchdog event occurred
369    #[inline(always)]
370    pub fn is_event(&self) -> bool {
371        *self == AWD1R::Event
372    }
373}
374/**Analog watchdog %s flag
375
376Value on reset: 0*/
377#[cfg_attr(feature = "defmt", derive(defmt::Format))]
378#[derive(Clone, Copy, Debug, PartialEq, Eq)]
379pub enum AWD1W {
380    ///1: Clear the analog watchdog event flag
381    Clear = 1,
382}
383impl From<AWD1W> for bool {
384    #[inline(always)]
385    fn from(variant: AWD1W) -> Self {
386        variant as u8 != 0
387    }
388}
389///Field `AWD(1-3)` writer - Analog watchdog %s flag
390pub type AWD_W<'a, REG> = crate::BitWriter1C<'a, REG, AWD1W>;
391impl<'a, REG> AWD_W<'a, REG>
392where
393    REG: crate::Writable + crate::RegisterSpec,
394{
395    ///Clear the analog watchdog event flag
396    #[inline(always)]
397    pub fn clear(self) -> &'a mut crate::W<REG> {
398        self.variant(AWD1W::Clear)
399    }
400}
401/**End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
402
403Value on reset: 0*/
404#[cfg_attr(feature = "defmt", derive(defmt::Format))]
405#[derive(Clone, Copy, Debug, PartialEq, Eq)]
406pub enum EOCALR {
407    ///0: Calibration is not complete
408    NotComplete = 0,
409    ///1: Calibration complete
410    Complete = 1,
411}
412impl From<EOCALR> for bool {
413    #[inline(always)]
414    fn from(variant: EOCALR) -> Self {
415        variant as u8 != 0
416    }
417}
418///Field `EOCAL` reader - End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
419pub type EOCAL_R = crate::BitReader<EOCALR>;
420impl EOCAL_R {
421    ///Get enumerated values variant
422    #[inline(always)]
423    pub const fn variant(&self) -> EOCALR {
424        match self.bits {
425            false => EOCALR::NotComplete,
426            true => EOCALR::Complete,
427        }
428    }
429    ///Calibration is not complete
430    #[inline(always)]
431    pub fn is_not_complete(&self) -> bool {
432        *self == EOCALR::NotComplete
433    }
434    ///Calibration complete
435    #[inline(always)]
436    pub fn is_complete(&self) -> bool {
437        *self == EOCALR::Complete
438    }
439}
440/**End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
441
442Value on reset: 0*/
443#[cfg_attr(feature = "defmt", derive(defmt::Format))]
444#[derive(Clone, Copy, Debug, PartialEq, Eq)]
445pub enum EOCALW {
446    ///1: Clear the calibration flag
447    Clear = 1,
448}
449impl From<EOCALW> for bool {
450    #[inline(always)]
451    fn from(variant: EOCALW) -> Self {
452        variant as u8 != 0
453    }
454}
455///Field `EOCAL` writer - End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
456pub type EOCAL_W<'a, REG> = crate::BitWriter1C<'a, REG, EOCALW>;
457impl<'a, REG> EOCAL_W<'a, REG>
458where
459    REG: crate::Writable + crate::RegisterSpec,
460{
461    ///Clear the calibration flag
462    #[inline(always)]
463    pub fn clear(self) -> &'a mut crate::W<REG> {
464        self.variant(EOCALW::Clear)
465    }
466}
467/**Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
468
469Value on reset: 0*/
470#[cfg_attr(feature = "defmt", derive(defmt::Format))]
471#[derive(Clone, Copy, Debug, PartialEq, Eq)]
472pub enum CCRDYR {
473    ///0: Channel configuration update not applied
474    NotComplete = 0,
475    ///1: Channel configuration update is applied
476    Complete = 1,
477}
478impl From<CCRDYR> for bool {
479    #[inline(always)]
480    fn from(variant: CCRDYR) -> Self {
481        variant as u8 != 0
482    }
483}
484///Field `CCRDY` reader - Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
485pub type CCRDY_R = crate::BitReader<CCRDYR>;
486impl CCRDY_R {
487    ///Get enumerated values variant
488    #[inline(always)]
489    pub const fn variant(&self) -> CCRDYR {
490        match self.bits {
491            false => CCRDYR::NotComplete,
492            true => CCRDYR::Complete,
493        }
494    }
495    ///Channel configuration update not applied
496    #[inline(always)]
497    pub fn is_not_complete(&self) -> bool {
498        *self == CCRDYR::NotComplete
499    }
500    ///Channel configuration update is applied
501    #[inline(always)]
502    pub fn is_complete(&self) -> bool {
503        *self == CCRDYR::Complete
504    }
505}
506/**Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
507
508Value on reset: 0*/
509#[cfg_attr(feature = "defmt", derive(defmt::Format))]
510#[derive(Clone, Copy, Debug, PartialEq, Eq)]
511pub enum CCRDYW {
512    ///1: Clear the channel configuration flag
513    Clear = 1,
514}
515impl From<CCRDYW> for bool {
516    #[inline(always)]
517    fn from(variant: CCRDYW) -> Self {
518        variant as u8 != 0
519    }
520}
521///Field `CCRDY` writer - Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
522pub type CCRDY_W<'a, REG> = crate::BitWriter1C<'a, REG, CCRDYW>;
523impl<'a, REG> CCRDY_W<'a, REG>
524where
525    REG: crate::Writable + crate::RegisterSpec,
526{
527    ///Clear the channel configuration flag
528    #[inline(always)]
529    pub fn clear(self) -> &'a mut crate::W<REG> {
530        self.variant(CCRDYW::Clear)
531    }
532}
533impl R {
534    ///Bit 0 - ADC ready This bit is set by hardware after the ADC has been enabled (ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
535    #[inline(always)]
536    pub fn adrdy(&self) -> ADRDY_R {
537        ADRDY_R::new((self.bits & 1) != 0)
538    }
539    ///Bit 1 - End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1'.
540    #[inline(always)]
541    pub fn eosmp(&self) -> EOSMP_R {
542        EOSMP_R::new(((self.bits >> 1) & 1) != 0)
543    }
544    ///Bit 2 - End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
545    #[inline(always)]
546    pub fn eoc(&self) -> EOC_R {
547        EOC_R::new(((self.bits >> 2) & 1) != 0)
548    }
549    ///Bit 3 - End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
550    #[inline(always)]
551    pub fn eos(&self) -> EOS_R {
552        EOS_R::new(((self.bits >> 3) & 1) != 0)
553    }
554    ///Bit 4 - ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
555    #[inline(always)]
556    pub fn ovr(&self) -> OVR_R {
557        OVR_R::new(((self.bits >> 4) & 1) != 0)
558    }
559    ///Analog watchdog (1-3) flag
560    ///
561    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD1` field.</div>
562    #[inline(always)]
563    pub fn awd(&self, n: u8) -> AWD_R {
564        #[allow(clippy::no_effect)]
565        [(); 3][n as usize];
566        AWD_R::new(((self.bits >> (n + 7)) & 1) != 0)
567    }
568    ///Iterator for array of:
569    ///Analog watchdog (1-3) flag
570    #[inline(always)]
571    pub fn awd_iter(&self) -> impl Iterator<Item = AWD_R> + '_ {
572        (0..3).map(move |n| AWD_R::new(((self.bits >> (n + 7)) & 1) != 0))
573    }
574    ///Bit 7 - Analog watchdog 1 flag
575    #[inline(always)]
576    pub fn awd1(&self) -> AWD_R {
577        AWD_R::new(((self.bits >> 7) & 1) != 0)
578    }
579    ///Bit 8 - Analog watchdog 2 flag
580    #[inline(always)]
581    pub fn awd2(&self) -> AWD_R {
582        AWD_R::new(((self.bits >> 8) & 1) != 0)
583    }
584    ///Bit 9 - Analog watchdog 3 flag
585    #[inline(always)]
586    pub fn awd3(&self) -> AWD_R {
587        AWD_R::new(((self.bits >> 9) & 1) != 0)
588    }
589    ///Bit 11 - End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
590    #[inline(always)]
591    pub fn eocal(&self) -> EOCAL_R {
592        EOCAL_R::new(((self.bits >> 11) & 1) != 0)
593    }
594    ///Bit 13 - Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
595    #[inline(always)]
596    pub fn ccrdy(&self) -> CCRDY_R {
597        CCRDY_R::new(((self.bits >> 13) & 1) != 0)
598    }
599}
600impl core::fmt::Debug for R {
601    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
602        f.debug_struct("ISR")
603            .field("adrdy", &self.adrdy())
604            .field("eosmp", &self.eosmp())
605            .field("eoc", &self.eoc())
606            .field("eos", &self.eos())
607            .field("ovr", &self.ovr())
608            .field("awd1", &self.awd1())
609            .field("awd2", &self.awd2())
610            .field("awd3", &self.awd3())
611            .field("eocal", &self.eocal())
612            .field("ccrdy", &self.ccrdy())
613            .finish()
614    }
615}
616impl W {
617    ///Bit 0 - ADC ready This bit is set by hardware after the ADC has been enabled (ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it.
618    #[inline(always)]
619    pub fn adrdy(&mut self) -> ADRDY_W<ISRrs> {
620        ADRDY_W::new(self, 0)
621    }
622    ///Bit 1 - End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1'.
623    #[inline(always)]
624    pub fn eosmp(&mut self) -> EOSMP_W<ISRrs> {
625        EOSMP_W::new(self, 1)
626    }
627    ///Bit 2 - End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.
628    #[inline(always)]
629    pub fn eoc(&mut self) -> EOC_W<ISRrs> {
630        EOC_W::new(self, 2)
631    }
632    ///Bit 3 - End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.
633    #[inline(always)]
634    pub fn eos(&mut self) -> EOS_W<ISRrs> {
635        EOS_W::new(self, 3)
636    }
637    ///Bit 4 - ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.
638    #[inline(always)]
639    pub fn ovr(&mut self) -> OVR_W<ISRrs> {
640        OVR_W::new(self, 4)
641    }
642    ///Analog watchdog (1-3) flag
643    ///
644    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `AWD1` field.</div>
645    #[inline(always)]
646    pub fn awd(&mut self, n: u8) -> AWD_W<ISRrs> {
647        #[allow(clippy::no_effect)]
648        [(); 3][n as usize];
649        AWD_W::new(self, n + 7)
650    }
651    ///Bit 7 - Analog watchdog 1 flag
652    #[inline(always)]
653    pub fn awd1(&mut self) -> AWD_W<ISRrs> {
654        AWD_W::new(self, 7)
655    }
656    ///Bit 8 - Analog watchdog 2 flag
657    #[inline(always)]
658    pub fn awd2(&mut self) -> AWD_W<ISRrs> {
659        AWD_W::new(self, 8)
660    }
661    ///Bit 9 - Analog watchdog 3 flag
662    #[inline(always)]
663    pub fn awd3(&mut self) -> AWD_W<ISRrs> {
664        AWD_W::new(self, 9)
665    }
666    ///Bit 11 - End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
667    #[inline(always)]
668    pub fn eocal(&mut self) -> EOCAL_W<ISRrs> {
669        EOCAL_W::new(self, 11)
670    }
671    ///Bit 13 - Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration.
672    #[inline(always)]
673    pub fn ccrdy(&mut self) -> CCRDY_W<ISRrs> {
674        CCRDY_W::new(self, 13)
675    }
676}
677/**ADC interrupt and status register
678
679You can [`read`](crate::Reg::read) this register and get [`isr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
680
681See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#ADC:ISR)*/
682pub struct ISRrs;
683impl crate::RegisterSpec for ISRrs {
684    type Ux = u32;
685}
686///`read()` method returns [`isr::R`](R) reader structure
687impl crate::Readable for ISRrs {}
688///`write(|w| ..)` method takes [`isr::W`](W) writer structure
689impl crate::Writable for ISRrs {
690    type Safety = crate::Unsafe;
691    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x2b9f;
692}
693///`reset()` method sets ISR to value 0
694impl crate::Resettable for ISRrs {}
stm32g0/stm32g0c1/adc/isr.rs

stm32g0/stm32g0c1/adc/
isr.rs
