stm32g0/stm32g0c1/adc/
cfgr2.rs

1///Register `CFGR2` reader
2pub type R = crate::R<CFGR2rs>;
3///Register `CFGR2` writer
4pub type W = crate::W<CFGR2rs>;
5/**Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum OVSE {
11    ///0: Oversampler disabled
12    Disabled = 0,
13    ///1: Oversampler enabled
14    Enabled = 1,
15}
16impl From<OVSE> for bool {
17    #[inline(always)]
18    fn from(variant: OVSE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `OVSE` reader - Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
23pub type OVSE_R = crate::BitReader<OVSE>;
24impl OVSE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> OVSE {
28        match self.bits {
29            false => OVSE::Disabled,
30            true => OVSE::Enabled,
31        }
32    }
33    ///Oversampler disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == OVSE::Disabled
37    }
38    ///Oversampler enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == OVSE::Enabled
42    }
43}
44///Field `OVSE` writer - Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
45pub type OVSE_W<'a, REG> = crate::BitWriter<'a, REG, OVSE>;
46impl<'a, REG> OVSE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Oversampler disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(OVSE::Disabled)
54    }
55    ///Oversampler enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(OVSE::Enabled)
59    }
60}
61/**Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum OVSR {
68    ///0: 2x
69    Mul2 = 0,
70    ///1: 4x
71    Mul4 = 1,
72    ///2: 8x
73    Mul8 = 2,
74    ///3: 16x
75    Mul16 = 3,
76    ///4: 32x
77    Mul32 = 4,
78    ///5: 64x
79    Mul64 = 5,
80    ///6: 128x
81    Mul128 = 6,
82    ///7: 256x
83    Mul256 = 7,
84}
85impl From<OVSR> for u8 {
86    #[inline(always)]
87    fn from(variant: OVSR) -> Self {
88        variant as _
89    }
90}
91impl crate::FieldSpec for OVSR {
92    type Ux = u8;
93}
94impl crate::IsEnum for OVSR {}
95///Field `OVSR` reader - Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
96pub type OVSR_R = crate::FieldReader<OVSR>;
97impl OVSR_R {
98    ///Get enumerated values variant
99    #[inline(always)]
100    pub const fn variant(&self) -> OVSR {
101        match self.bits {
102            0 => OVSR::Mul2,
103            1 => OVSR::Mul4,
104            2 => OVSR::Mul8,
105            3 => OVSR::Mul16,
106            4 => OVSR::Mul32,
107            5 => OVSR::Mul64,
108            6 => OVSR::Mul128,
109            7 => OVSR::Mul256,
110            _ => unreachable!(),
111        }
112    }
113    ///2x
114    #[inline(always)]
115    pub fn is_mul2(&self) -> bool {
116        *self == OVSR::Mul2
117    }
118    ///4x
119    #[inline(always)]
120    pub fn is_mul4(&self) -> bool {
121        *self == OVSR::Mul4
122    }
123    ///8x
124    #[inline(always)]
125    pub fn is_mul8(&self) -> bool {
126        *self == OVSR::Mul8
127    }
128    ///16x
129    #[inline(always)]
130    pub fn is_mul16(&self) -> bool {
131        *self == OVSR::Mul16
132    }
133    ///32x
134    #[inline(always)]
135    pub fn is_mul32(&self) -> bool {
136        *self == OVSR::Mul32
137    }
138    ///64x
139    #[inline(always)]
140    pub fn is_mul64(&self) -> bool {
141        *self == OVSR::Mul64
142    }
143    ///128x
144    #[inline(always)]
145    pub fn is_mul128(&self) -> bool {
146        *self == OVSR::Mul128
147    }
148    ///256x
149    #[inline(always)]
150    pub fn is_mul256(&self) -> bool {
151        *self == OVSR::Mul256
152    }
153}
154///Field `OVSR` writer - Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
155pub type OVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 3, OVSR, crate::Safe>;
156impl<'a, REG> OVSR_W<'a, REG>
157where
158    REG: crate::Writable + crate::RegisterSpec,
159    REG::Ux: From<u8>,
160{
161    ///2x
162    #[inline(always)]
163    pub fn mul2(self) -> &'a mut crate::W<REG> {
164        self.variant(OVSR::Mul2)
165    }
166    ///4x
167    #[inline(always)]
168    pub fn mul4(self) -> &'a mut crate::W<REG> {
169        self.variant(OVSR::Mul4)
170    }
171    ///8x
172    #[inline(always)]
173    pub fn mul8(self) -> &'a mut crate::W<REG> {
174        self.variant(OVSR::Mul8)
175    }
176    ///16x
177    #[inline(always)]
178    pub fn mul16(self) -> &'a mut crate::W<REG> {
179        self.variant(OVSR::Mul16)
180    }
181    ///32x
182    #[inline(always)]
183    pub fn mul32(self) -> &'a mut crate::W<REG> {
184        self.variant(OVSR::Mul32)
185    }
186    ///64x
187    #[inline(always)]
188    pub fn mul64(self) -> &'a mut crate::W<REG> {
189        self.variant(OVSR::Mul64)
190    }
191    ///128x
192    #[inline(always)]
193    pub fn mul128(self) -> &'a mut crate::W<REG> {
194        self.variant(OVSR::Mul128)
195    }
196    ///256x
197    #[inline(always)]
198    pub fn mul256(self) -> &'a mut crate::W<REG> {
199        self.variant(OVSR::Mul256)
200    }
201}
202/**Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
203
204Value on reset: 0*/
205#[cfg_attr(feature = "defmt", derive(defmt::Format))]
206#[derive(Clone, Copy, Debug, PartialEq, Eq)]
207#[repr(u8)]
208pub enum OVSS {
209    ///0: No shift
210    NoShift = 0,
211    ///1: Shift 1-bit
212    Shift1 = 1,
213    ///2: Shift 2-bits
214    Shift2 = 2,
215    ///3: Shift 3-bits
216    Shift3 = 3,
217    ///4: Shift 4-bits
218    Shift4 = 4,
219    ///5: Shift 5-bits
220    Shift5 = 5,
221    ///6: Shift 6-bits
222    Shift6 = 6,
223    ///7: Shift 7-bits
224    Shift7 = 7,
225    ///8: Shift 8-bits
226    Shift8 = 8,
227}
228impl From<OVSS> for u8 {
229    #[inline(always)]
230    fn from(variant: OVSS) -> Self {
231        variant as _
232    }
233}
234impl crate::FieldSpec for OVSS {
235    type Ux = u8;
236}
237impl crate::IsEnum for OVSS {}
238///Field `OVSS` reader - Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
239pub type OVSS_R = crate::FieldReader<OVSS>;
240impl OVSS_R {
241    ///Get enumerated values variant
242    #[inline(always)]
243    pub const fn variant(&self) -> Option<OVSS> {
244        match self.bits {
245            0 => Some(OVSS::NoShift),
246            1 => Some(OVSS::Shift1),
247            2 => Some(OVSS::Shift2),
248            3 => Some(OVSS::Shift3),
249            4 => Some(OVSS::Shift4),
250            5 => Some(OVSS::Shift5),
251            6 => Some(OVSS::Shift6),
252            7 => Some(OVSS::Shift7),
253            8 => Some(OVSS::Shift8),
254            _ => None,
255        }
256    }
257    ///No shift
258    #[inline(always)]
259    pub fn is_no_shift(&self) -> bool {
260        *self == OVSS::NoShift
261    }
262    ///Shift 1-bit
263    #[inline(always)]
264    pub fn is_shift1(&self) -> bool {
265        *self == OVSS::Shift1
266    }
267    ///Shift 2-bits
268    #[inline(always)]
269    pub fn is_shift2(&self) -> bool {
270        *self == OVSS::Shift2
271    }
272    ///Shift 3-bits
273    #[inline(always)]
274    pub fn is_shift3(&self) -> bool {
275        *self == OVSS::Shift3
276    }
277    ///Shift 4-bits
278    #[inline(always)]
279    pub fn is_shift4(&self) -> bool {
280        *self == OVSS::Shift4
281    }
282    ///Shift 5-bits
283    #[inline(always)]
284    pub fn is_shift5(&self) -> bool {
285        *self == OVSS::Shift5
286    }
287    ///Shift 6-bits
288    #[inline(always)]
289    pub fn is_shift6(&self) -> bool {
290        *self == OVSS::Shift6
291    }
292    ///Shift 7-bits
293    #[inline(always)]
294    pub fn is_shift7(&self) -> bool {
295        *self == OVSS::Shift7
296    }
297    ///Shift 8-bits
298    #[inline(always)]
299    pub fn is_shift8(&self) -> bool {
300        *self == OVSS::Shift8
301    }
302}
303///Field `OVSS` writer - Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
304pub type OVSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4, OVSS>;
305impl<'a, REG> OVSS_W<'a, REG>
306where
307    REG: crate::Writable + crate::RegisterSpec,
308    REG::Ux: From<u8>,
309{
310    ///No shift
311    #[inline(always)]
312    pub fn no_shift(self) -> &'a mut crate::W<REG> {
313        self.variant(OVSS::NoShift)
314    }
315    ///Shift 1-bit
316    #[inline(always)]
317    pub fn shift1(self) -> &'a mut crate::W<REG> {
318        self.variant(OVSS::Shift1)
319    }
320    ///Shift 2-bits
321    #[inline(always)]
322    pub fn shift2(self) -> &'a mut crate::W<REG> {
323        self.variant(OVSS::Shift2)
324    }
325    ///Shift 3-bits
326    #[inline(always)]
327    pub fn shift3(self) -> &'a mut crate::W<REG> {
328        self.variant(OVSS::Shift3)
329    }
330    ///Shift 4-bits
331    #[inline(always)]
332    pub fn shift4(self) -> &'a mut crate::W<REG> {
333        self.variant(OVSS::Shift4)
334    }
335    ///Shift 5-bits
336    #[inline(always)]
337    pub fn shift5(self) -> &'a mut crate::W<REG> {
338        self.variant(OVSS::Shift5)
339    }
340    ///Shift 6-bits
341    #[inline(always)]
342    pub fn shift6(self) -> &'a mut crate::W<REG> {
343        self.variant(OVSS::Shift6)
344    }
345    ///Shift 7-bits
346    #[inline(always)]
347    pub fn shift7(self) -> &'a mut crate::W<REG> {
348        self.variant(OVSS::Shift7)
349    }
350    ///Shift 8-bits
351    #[inline(always)]
352    pub fn shift8(self) -> &'a mut crate::W<REG> {
353        self.variant(OVSS::Shift8)
354    }
355}
356/**Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
357
358Value on reset: 0*/
359#[cfg_attr(feature = "defmt", derive(defmt::Format))]
360#[derive(Clone, Copy, Debug, PartialEq, Eq)]
361pub enum TOVS {
362    ///0: All oversampled conversions for a channel are done consecutively after a trigger
363    TriggerAll = 0,
364    ///1: Each oversampled conversion for a channel needs a trigger
365    TriggerEach = 1,
366}
367impl From<TOVS> for bool {
368    #[inline(always)]
369    fn from(variant: TOVS) -> Self {
370        variant as u8 != 0
371    }
372}
373///Field `TOVS` reader - Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
374pub type TOVS_R = crate::BitReader<TOVS>;
375impl TOVS_R {
376    ///Get enumerated values variant
377    #[inline(always)]
378    pub const fn variant(&self) -> TOVS {
379        match self.bits {
380            false => TOVS::TriggerAll,
381            true => TOVS::TriggerEach,
382        }
383    }
384    ///All oversampled conversions for a channel are done consecutively after a trigger
385    #[inline(always)]
386    pub fn is_trigger_all(&self) -> bool {
387        *self == TOVS::TriggerAll
388    }
389    ///Each oversampled conversion for a channel needs a trigger
390    #[inline(always)]
391    pub fn is_trigger_each(&self) -> bool {
392        *self == TOVS::TriggerEach
393    }
394}
395///Field `TOVS` writer - Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
396pub type TOVS_W<'a, REG> = crate::BitWriter<'a, REG, TOVS>;
397impl<'a, REG> TOVS_W<'a, REG>
398where
399    REG: crate::Writable + crate::RegisterSpec,
400{
401    ///All oversampled conversions for a channel are done consecutively after a trigger
402    #[inline(always)]
403    pub fn trigger_all(self) -> &'a mut crate::W<REG> {
404        self.variant(TOVS::TriggerAll)
405    }
406    ///Each oversampled conversion for a channel needs a trigger
407    #[inline(always)]
408    pub fn trigger_each(self) -> &'a mut crate::W<REG> {
409        self.variant(TOVS::TriggerEach)
410    }
411}
412/**Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
413
414Value on reset: 0*/
415#[cfg_attr(feature = "defmt", derive(defmt::Format))]
416#[derive(Clone, Copy, Debug, PartialEq, Eq)]
417pub enum LFTRIG {
418    ///0: Low Frequency Trigger Mode disabled
419    Disabled = 0,
420    ///1: Low Frequency Trigger Mode enabled
421    Enabled = 1,
422}
423impl From<LFTRIG> for bool {
424    #[inline(always)]
425    fn from(variant: LFTRIG) -> Self {
426        variant as u8 != 0
427    }
428}
429///Field `LFTRIG` reader - Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
430pub type LFTRIG_R = crate::BitReader<LFTRIG>;
431impl LFTRIG_R {
432    ///Get enumerated values variant
433    #[inline(always)]
434    pub const fn variant(&self) -> LFTRIG {
435        match self.bits {
436            false => LFTRIG::Disabled,
437            true => LFTRIG::Enabled,
438        }
439    }
440    ///Low Frequency Trigger Mode disabled
441    #[inline(always)]
442    pub fn is_disabled(&self) -> bool {
443        *self == LFTRIG::Disabled
444    }
445    ///Low Frequency Trigger Mode enabled
446    #[inline(always)]
447    pub fn is_enabled(&self) -> bool {
448        *self == LFTRIG::Enabled
449    }
450}
451///Field `LFTRIG` writer - Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
452pub type LFTRIG_W<'a, REG> = crate::BitWriter<'a, REG, LFTRIG>;
453impl<'a, REG> LFTRIG_W<'a, REG>
454where
455    REG: crate::Writable + crate::RegisterSpec,
456{
457    ///Low Frequency Trigger Mode disabled
458    #[inline(always)]
459    pub fn disabled(self) -> &'a mut crate::W<REG> {
460        self.variant(LFTRIG::Disabled)
461    }
462    ///Low Frequency Trigger Mode enabled
463    #[inline(always)]
464    pub fn enabled(self) -> &'a mut crate::W<REG> {
465        self.variant(LFTRIG::Enabled)
466    }
467}
468/**ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
469
470Value on reset: 0*/
471#[cfg_attr(feature = "defmt", derive(defmt::Format))]
472#[derive(Clone, Copy, Debug, PartialEq, Eq)]
473#[repr(u8)]
474pub enum CKMODE {
475    ///0: ADCCLK (Asynchronous clock mode)
476    Adclk = 0,
477    ///1: PCLK/2 (Synchronous clock mode)
478    PclkDiv2 = 1,
479    ///2: PCLK/4 (Synchronous clock mode)
480    PclkDiv4 = 2,
481    ///3: PCLK (Synchronous clock mode)
482    Pclk = 3,
483}
484impl From<CKMODE> for u8 {
485    #[inline(always)]
486    fn from(variant: CKMODE) -> Self {
487        variant as _
488    }
489}
490impl crate::FieldSpec for CKMODE {
491    type Ux = u8;
492}
493impl crate::IsEnum for CKMODE {}
494///Field `CKMODE` reader - ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
495pub type CKMODE_R = crate::FieldReader<CKMODE>;
496impl CKMODE_R {
497    ///Get enumerated values variant
498    #[inline(always)]
499    pub const fn variant(&self) -> CKMODE {
500        match self.bits {
501            0 => CKMODE::Adclk,
502            1 => CKMODE::PclkDiv2,
503            2 => CKMODE::PclkDiv4,
504            3 => CKMODE::Pclk,
505            _ => unreachable!(),
506        }
507    }
508    ///ADCCLK (Asynchronous clock mode)
509    #[inline(always)]
510    pub fn is_adclk(&self) -> bool {
511        *self == CKMODE::Adclk
512    }
513    ///PCLK/2 (Synchronous clock mode)
514    #[inline(always)]
515    pub fn is_pclk_div2(&self) -> bool {
516        *self == CKMODE::PclkDiv2
517    }
518    ///PCLK/4 (Synchronous clock mode)
519    #[inline(always)]
520    pub fn is_pclk_div4(&self) -> bool {
521        *self == CKMODE::PclkDiv4
522    }
523    ///PCLK (Synchronous clock mode)
524    #[inline(always)]
525    pub fn is_pclk(&self) -> bool {
526        *self == CKMODE::Pclk
527    }
528}
529///Field `CKMODE` writer - ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
530pub type CKMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CKMODE, crate::Safe>;
531impl<'a, REG> CKMODE_W<'a, REG>
532where
533    REG: crate::Writable + crate::RegisterSpec,
534    REG::Ux: From<u8>,
535{
536    ///ADCCLK (Asynchronous clock mode)
537    #[inline(always)]
538    pub fn adclk(self) -> &'a mut crate::W<REG> {
539        self.variant(CKMODE::Adclk)
540    }
541    ///PCLK/2 (Synchronous clock mode)
542    #[inline(always)]
543    pub fn pclk_div2(self) -> &'a mut crate::W<REG> {
544        self.variant(CKMODE::PclkDiv2)
545    }
546    ///PCLK/4 (Synchronous clock mode)
547    #[inline(always)]
548    pub fn pclk_div4(self) -> &'a mut crate::W<REG> {
549        self.variant(CKMODE::PclkDiv4)
550    }
551    ///PCLK (Synchronous clock mode)
552    #[inline(always)]
553    pub fn pclk(self) -> &'a mut crate::W<REG> {
554        self.variant(CKMODE::Pclk)
555    }
556}
557impl R {
558    ///Bit 0 - Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
559    #[inline(always)]
560    pub fn ovse(&self) -> OVSE_R {
561        OVSE_R::new((self.bits & 1) != 0)
562    }
563    ///Bits 2:4 - Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
564    #[inline(always)]
565    pub fn ovsr(&self) -> OVSR_R {
566        OVSR_R::new(((self.bits >> 2) & 7) as u8)
567    }
568    ///Bits 5:8 - Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
569    #[inline(always)]
570    pub fn ovss(&self) -> OVSS_R {
571        OVSS_R::new(((self.bits >> 5) & 0x0f) as u8)
572    }
573    ///Bit 9 - Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
574    #[inline(always)]
575    pub fn tovs(&self) -> TOVS_R {
576        TOVS_R::new(((self.bits >> 9) & 1) != 0)
577    }
578    ///Bit 29 - Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
579    #[inline(always)]
580    pub fn lftrig(&self) -> LFTRIG_R {
581        LFTRIG_R::new(((self.bits >> 29) & 1) != 0)
582    }
583    ///Bits 30:31 - ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
584    #[inline(always)]
585    pub fn ckmode(&self) -> CKMODE_R {
586        CKMODE_R::new(((self.bits >> 30) & 3) as u8)
587    }
588}
589impl core::fmt::Debug for R {
590    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
591        f.debug_struct("CFGR2")
592            .field("ovse", &self.ovse())
593            .field("ovsr", &self.ovsr())
594            .field("ovss", &self.ovss())
595            .field("tovs", &self.tovs())
596            .field("lftrig", &self.lftrig())
597            .field("ckmode", &self.ckmode())
598            .finish()
599    }
600}
601impl W {
602    ///Bit 0 - Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
603    #[inline(always)]
604    pub fn ovse(&mut self) -> OVSE_W<CFGR2rs> {
605        OVSE_W::new(self, 0)
606    }
607    ///Bits 2:4 - Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
608    #[inline(always)]
609    pub fn ovsr(&mut self) -> OVSR_W<CFGR2rs> {
610        OVSR_W::new(self, 2)
611    }
612    ///Bits 5:8 - Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
613    #[inline(always)]
614    pub fn ovss(&mut self) -> OVSS_W<CFGR2rs> {
615        OVSS_W::new(self, 5)
616    }
617    ///Bit 9 - Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
618    #[inline(always)]
619    pub fn tovs(&mut self) -> TOVS_W<CFGR2rs> {
620        TOVS_W::new(self, 9)
621    }
622    ///Bit 29 - Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing).
623    #[inline(always)]
624    pub fn lftrig(&mut self) -> LFTRIG_W<CFGR2rs> {
625        LFTRIG_W::new(self, 29)
626    }
627    ///Bits 30:31 - ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
628    #[inline(always)]
629    pub fn ckmode(&mut self) -> CKMODE_W<CFGR2rs> {
630        CKMODE_W::new(self, 30)
631    }
632}
633/**ADC configuration register 2
634
635You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
636
637See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#ADC:CFGR2)*/
638pub struct CFGR2rs;
639impl crate::RegisterSpec for CFGR2rs {
640    type Ux = u32;
641}
642///`read()` method returns [`cfgr2::R`](R) reader structure
643impl crate::Readable for CFGR2rs {}
644///`write(|w| ..)` method takes [`cfgr2::W`](W) writer structure
645impl crate::Writable for CFGR2rs {
646    type Safety = crate::Unsafe;
647}
648///`reset()` method sets CFGR2 to value 0
649impl crate::Resettable for CFGR2rs {}
stm32g0/stm32g0c1/adc/cfgr2.rs

stm32g0/stm32g0c1/adc/
cfgr2.rs
