stm32g0/stm32g0b0/tim16/
bdtr.rs

1///Register `BDTR` reader
2pub type R = crate::R<BDTRrs>;
3///Register `BDTR` writer
4pub type W = crate::W<BDTRrs>;
5///Field `DTG` reader - Dead-time generator setup
6pub type DTG_R = crate::FieldReader;
7///Field `DTG` writer - Dead-time generator setup
8pub type DTG_W<'a, REG> = crate::FieldWriter<'a, REG, 8, u8, crate::Safe>;
9/**Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14#[repr(u8)]
15pub enum LOCK {
16    ///0: No bit is write protected
17    Off = 0,
18    ///1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
19    Level1 = 1,
20    ///2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
21    Level2 = 2,
22    ///3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
23    Level3 = 3,
24}
25impl From<LOCK> for u8 {
26    #[inline(always)]
27    fn from(variant: LOCK) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for LOCK {
32    type Ux = u8;
33}
34impl crate::IsEnum for LOCK {}
35///Field `LOCK` reader - Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
36pub type LOCK_R = crate::FieldReader<LOCK>;
37impl LOCK_R {
38    ///Get enumerated values variant
39    #[inline(always)]
40    pub const fn variant(&self) -> LOCK {
41        match self.bits {
42            0 => LOCK::Off,
43            1 => LOCK::Level1,
44            2 => LOCK::Level2,
45            3 => LOCK::Level3,
46            _ => unreachable!(),
47        }
48    }
49    ///No bit is write protected
50    #[inline(always)]
51    pub fn is_off(&self) -> bool {
52        *self == LOCK::Off
53    }
54    ///Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
55    #[inline(always)]
56    pub fn is_level1(&self) -> bool {
57        *self == LOCK::Level1
58    }
59    ///LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
60    #[inline(always)]
61    pub fn is_level2(&self) -> bool {
62        *self == LOCK::Level2
63    }
64    ///LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
65    #[inline(always)]
66    pub fn is_level3(&self) -> bool {
67        *self == LOCK::Level3
68    }
69}
70///Field `LOCK` writer - Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
71pub type LOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LOCK, crate::Safe>;
72impl<'a, REG> LOCK_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    ///No bit is write protected
78    #[inline(always)]
79    pub fn off(self) -> &'a mut crate::W<REG> {
80        self.variant(LOCK::Off)
81    }
82    ///Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
83    #[inline(always)]
84    pub fn level1(self) -> &'a mut crate::W<REG> {
85        self.variant(LOCK::Level1)
86    }
87    ///LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
88    #[inline(always)]
89    pub fn level2(self) -> &'a mut crate::W<REG> {
90        self.variant(LOCK::Level2)
91    }
92    ///LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
93    #[inline(always)]
94    pub fn level3(self) -> &'a mut crate::W<REG> {
95        self.variant(LOCK::Level3)
96    }
97}
98/**Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
99
100Value on reset: 0*/
101#[cfg_attr(feature = "defmt", derive(defmt::Format))]
102#[derive(Clone, Copy, Debug, PartialEq, Eq)]
103pub enum OSSI {
104    ///0: When inactive, OC/OCN outputs are disabled
105    HiZ = 0,
106    ///1: When inactive, OC/OCN outputs are forced to idle level
107    IdleLevel = 1,
108}
109impl From<OSSI> for bool {
110    #[inline(always)]
111    fn from(variant: OSSI) -> Self {
112        variant as u8 != 0
113    }
114}
115///Field `OSSI` reader - Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
116pub type OSSI_R = crate::BitReader<OSSI>;
117impl OSSI_R {
118    ///Get enumerated values variant
119    #[inline(always)]
120    pub const fn variant(&self) -> OSSI {
121        match self.bits {
122            false => OSSI::HiZ,
123            true => OSSI::IdleLevel,
124        }
125    }
126    ///When inactive, OC/OCN outputs are disabled
127    #[inline(always)]
128    pub fn is_hi_z(&self) -> bool {
129        *self == OSSI::HiZ
130    }
131    ///When inactive, OC/OCN outputs are forced to idle level
132    #[inline(always)]
133    pub fn is_idle_level(&self) -> bool {
134        *self == OSSI::IdleLevel
135    }
136}
137///Field `OSSI` writer - Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
138pub type OSSI_W<'a, REG> = crate::BitWriter<'a, REG, OSSI>;
139impl<'a, REG> OSSI_W<'a, REG>
140where
141    REG: crate::Writable + crate::RegisterSpec,
142{
143    ///When inactive, OC/OCN outputs are disabled
144    #[inline(always)]
145    pub fn hi_z(self) -> &'a mut crate::W<REG> {
146        self.variant(OSSI::HiZ)
147    }
148    ///When inactive, OC/OCN outputs are forced to idle level
149    #[inline(always)]
150    pub fn idle_level(self) -> &'a mut crate::W<REG> {
151        self.variant(OSSI::IdleLevel)
152    }
153}
154/**Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
155
156Value on reset: 0*/
157#[cfg_attr(feature = "defmt", derive(defmt::Format))]
158#[derive(Clone, Copy, Debug, PartialEq, Eq)]
159pub enum OSSR {
160    ///0: When inactive, OC/OCN outputs are disabled
161    HiZ = 0,
162    ///1: When inactive, OC/OCN outputs are enabled with their inactive level
163    IdleLevel = 1,
164}
165impl From<OSSR> for bool {
166    #[inline(always)]
167    fn from(variant: OSSR) -> Self {
168        variant as u8 != 0
169    }
170}
171///Field `OSSR` reader - Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
172pub type OSSR_R = crate::BitReader<OSSR>;
173impl OSSR_R {
174    ///Get enumerated values variant
175    #[inline(always)]
176    pub const fn variant(&self) -> OSSR {
177        match self.bits {
178            false => OSSR::HiZ,
179            true => OSSR::IdleLevel,
180        }
181    }
182    ///When inactive, OC/OCN outputs are disabled
183    #[inline(always)]
184    pub fn is_hi_z(&self) -> bool {
185        *self == OSSR::HiZ
186    }
187    ///When inactive, OC/OCN outputs are enabled with their inactive level
188    #[inline(always)]
189    pub fn is_idle_level(&self) -> bool {
190        *self == OSSR::IdleLevel
191    }
192}
193///Field `OSSR` writer - Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
194pub type OSSR_W<'a, REG> = crate::BitWriter<'a, REG, OSSR>;
195impl<'a, REG> OSSR_W<'a, REG>
196where
197    REG: crate::Writable + crate::RegisterSpec,
198{
199    ///When inactive, OC/OCN outputs are disabled
200    #[inline(always)]
201    pub fn hi_z(self) -> &'a mut crate::W<REG> {
202        self.variant(OSSR::HiZ)
203    }
204    ///When inactive, OC/OCN outputs are enabled with their inactive level
205    #[inline(always)]
206    pub fn idle_level(self) -> &'a mut crate::W<REG> {
207        self.variant(OSSR::IdleLevel)
208    }
209}
210/**Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
211
212Value on reset: 0*/
213#[cfg_attr(feature = "defmt", derive(defmt::Format))]
214#[derive(Clone, Copy, Debug, PartialEq, Eq)]
215pub enum BKE {
216    ///0: Break function x disabled
217    Disabled = 0,
218    ///1: Break function x enabled
219    Enabled = 1,
220}
221impl From<BKE> for bool {
222    #[inline(always)]
223    fn from(variant: BKE) -> Self {
224        variant as u8 != 0
225    }
226}
227///Field `BKE` reader - Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
228pub type BKE_R = crate::BitReader<BKE>;
229impl BKE_R {
230    ///Get enumerated values variant
231    #[inline(always)]
232    pub const fn variant(&self) -> BKE {
233        match self.bits {
234            false => BKE::Disabled,
235            true => BKE::Enabled,
236        }
237    }
238    ///Break function x disabled
239    #[inline(always)]
240    pub fn is_disabled(&self) -> bool {
241        *self == BKE::Disabled
242    }
243    ///Break function x enabled
244    #[inline(always)]
245    pub fn is_enabled(&self) -> bool {
246        *self == BKE::Enabled
247    }
248}
249///Field `BKE` writer - Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
250pub type BKE_W<'a, REG> = crate::BitWriter<'a, REG, BKE>;
251impl<'a, REG> BKE_W<'a, REG>
252where
253    REG: crate::Writable + crate::RegisterSpec,
254{
255    ///Break function x disabled
256    #[inline(always)]
257    pub fn disabled(self) -> &'a mut crate::W<REG> {
258        self.variant(BKE::Disabled)
259    }
260    ///Break function x enabled
261    #[inline(always)]
262    pub fn enabled(self) -> &'a mut crate::W<REG> {
263        self.variant(BKE::Enabled)
264    }
265}
266/**Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
267
268Value on reset: 0*/
269#[cfg_attr(feature = "defmt", derive(defmt::Format))]
270#[derive(Clone, Copy, Debug, PartialEq, Eq)]
271pub enum BKP {
272    ///0: Break input BRKx is active low
273    ActiveLow = 0,
274    ///1: Break input BRKx is active high
275    ActiveHigh = 1,
276}
277impl From<BKP> for bool {
278    #[inline(always)]
279    fn from(variant: BKP) -> Self {
280        variant as u8 != 0
281    }
282}
283///Field `BKP` reader - Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
284pub type BKP_R = crate::BitReader<BKP>;
285impl BKP_R {
286    ///Get enumerated values variant
287    #[inline(always)]
288    pub const fn variant(&self) -> BKP {
289        match self.bits {
290            false => BKP::ActiveLow,
291            true => BKP::ActiveHigh,
292        }
293    }
294    ///Break input BRKx is active low
295    #[inline(always)]
296    pub fn is_active_low(&self) -> bool {
297        *self == BKP::ActiveLow
298    }
299    ///Break input BRKx is active high
300    #[inline(always)]
301    pub fn is_active_high(&self) -> bool {
302        *self == BKP::ActiveHigh
303    }
304}
305///Field `BKP` writer - Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
306pub type BKP_W<'a, REG> = crate::BitWriter<'a, REG, BKP>;
307impl<'a, REG> BKP_W<'a, REG>
308where
309    REG: crate::Writable + crate::RegisterSpec,
310{
311    ///Break input BRKx is active low
312    #[inline(always)]
313    pub fn active_low(self) -> &'a mut crate::W<REG> {
314        self.variant(BKP::ActiveLow)
315    }
316    ///Break input BRKx is active high
317    #[inline(always)]
318    pub fn active_high(self) -> &'a mut crate::W<REG> {
319        self.variant(BKP::ActiveHigh)
320    }
321}
322/**Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
323
324Value on reset: 0*/
325#[cfg_attr(feature = "defmt", derive(defmt::Format))]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum AOE {
328    ///0: MOE can be set only by software
329    Manual = 0,
330    ///1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
331    Automatic = 1,
332}
333impl From<AOE> for bool {
334    #[inline(always)]
335    fn from(variant: AOE) -> Self {
336        variant as u8 != 0
337    }
338}
339///Field `AOE` reader - Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
340pub type AOE_R = crate::BitReader<AOE>;
341impl AOE_R {
342    ///Get enumerated values variant
343    #[inline(always)]
344    pub const fn variant(&self) -> AOE {
345        match self.bits {
346            false => AOE::Manual,
347            true => AOE::Automatic,
348        }
349    }
350    ///MOE can be set only by software
351    #[inline(always)]
352    pub fn is_manual(&self) -> bool {
353        *self == AOE::Manual
354    }
355    ///MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
356    #[inline(always)]
357    pub fn is_automatic(&self) -> bool {
358        *self == AOE::Automatic
359    }
360}
361///Field `AOE` writer - Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
362pub type AOE_W<'a, REG> = crate::BitWriter<'a, REG, AOE>;
363impl<'a, REG> AOE_W<'a, REG>
364where
365    REG: crate::Writable + crate::RegisterSpec,
366{
367    ///MOE can be set only by software
368    #[inline(always)]
369    pub fn manual(self) -> &'a mut crate::W<REG> {
370        self.variant(AOE::Manual)
371    }
372    ///MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
373    #[inline(always)]
374    pub fn automatic(self) -> &'a mut crate::W<REG> {
375        self.variant(AOE::Automatic)
376    }
377}
378/**Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846).
379
380Value on reset: 0*/
381#[cfg_attr(feature = "defmt", derive(defmt::Format))]
382#[derive(Clone, Copy, Debug, PartialEq, Eq)]
383pub enum MOE {
384    ///0: OC/OCN are disabled or forced idle depending on OSSI
385    DisabledIdle = 0,
386    ///1: OC/OCN are enabled if CCxE/CCxNE are set
387    Enabled = 1,
388}
389impl From<MOE> for bool {
390    #[inline(always)]
391    fn from(variant: MOE) -> Self {
392        variant as u8 != 0
393    }
394}
395///Field `MOE` reader - Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846).
396pub type MOE_R = crate::BitReader<MOE>;
397impl MOE_R {
398    ///Get enumerated values variant
399    #[inline(always)]
400    pub const fn variant(&self) -> MOE {
401        match self.bits {
402            false => MOE::DisabledIdle,
403            true => MOE::Enabled,
404        }
405    }
406    ///OC/OCN are disabled or forced idle depending on OSSI
407    #[inline(always)]
408    pub fn is_disabled_idle(&self) -> bool {
409        *self == MOE::DisabledIdle
410    }
411    ///OC/OCN are enabled if CCxE/CCxNE are set
412    #[inline(always)]
413    pub fn is_enabled(&self) -> bool {
414        *self == MOE::Enabled
415    }
416}
417///Field `MOE` writer - Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846).
418pub type MOE_W<'a, REG> = crate::BitWriter<'a, REG, MOE>;
419impl<'a, REG> MOE_W<'a, REG>
420where
421    REG: crate::Writable + crate::RegisterSpec,
422{
423    ///OC/OCN are disabled or forced idle depending on OSSI
424    #[inline(always)]
425    pub fn disabled_idle(self) -> &'a mut crate::W<REG> {
426        self.variant(MOE::DisabledIdle)
427    }
428    ///OC/OCN are enabled if CCxE/CCxNE are set
429    #[inline(always)]
430    pub fn enabled(self) -> &'a mut crate::W<REG> {
431        self.variant(MOE::Enabled)
432    }
433}
434///Field `BKF` reader - Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
435pub type BKF_R = crate::FieldReader;
436///Field `BKF` writer - Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
437pub type BKF_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
438///Field `BKDSRM` reader - Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
439pub type BKDSRM_R = crate::BitReader;
440///Field `BKDSRM` writer - Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
441pub type BKDSRM_W<'a, REG> = crate::BitWriter<'a, REG>;
442///Field `BKBID` reader - Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
443pub type BKBID_R = crate::BitReader;
444///Field `BKBID` writer - Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
445pub type BKBID_W<'a, REG> = crate::BitWriter<'a, REG>;
446impl R {
447    ///Bits 0:7 - Dead-time generator setup
448    #[inline(always)]
449    pub fn dtg(&self) -> DTG_R {
450        DTG_R::new((self.bits & 0xff) as u8)
451    }
452    ///Bits 8:9 - Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
453    #[inline(always)]
454    pub fn lock(&self) -> LOCK_R {
455        LOCK_R::new(((self.bits >> 8) & 3) as u8)
456    }
457    ///Bit 10 - Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
458    #[inline(always)]
459    pub fn ossi(&self) -> OSSI_R {
460        OSSI_R::new(((self.bits >> 10) & 1) != 0)
461    }
462    ///Bit 11 - Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
463    #[inline(always)]
464    pub fn ossr(&self) -> OSSR_R {
465        OSSR_R::new(((self.bits >> 11) & 1) != 0)
466    }
467    ///Bit 12 - Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
468    #[inline(always)]
469    pub fn bke(&self) -> BKE_R {
470        BKE_R::new(((self.bits >> 12) & 1) != 0)
471    }
472    ///Bit 13 - Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
473    #[inline(always)]
474    pub fn bkp(&self) -> BKP_R {
475        BKP_R::new(((self.bits >> 13) & 1) != 0)
476    }
477    ///Bit 14 - Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
478    #[inline(always)]
479    pub fn aoe(&self) -> AOE_R {
480        AOE_R::new(((self.bits >> 14) & 1) != 0)
481    }
482    ///Bit 15 - Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846).
483    #[inline(always)]
484    pub fn moe(&self) -> MOE_R {
485        MOE_R::new(((self.bits >> 15) & 1) != 0)
486    }
487    ///Bits 16:19 - Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
488    #[inline(always)]
489    pub fn bkf(&self) -> BKF_R {
490        BKF_R::new(((self.bits >> 16) & 0x0f) as u8)
491    }
492    ///Bit 26 - Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
493    #[inline(always)]
494    pub fn bkdsrm(&self) -> BKDSRM_R {
495        BKDSRM_R::new(((self.bits >> 26) & 1) != 0)
496    }
497    ///Bit 28 - Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
498    #[inline(always)]
499    pub fn bkbid(&self) -> BKBID_R {
500        BKBID_R::new(((self.bits >> 28) & 1) != 0)
501    }
502}
503impl core::fmt::Debug for R {
504    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
505        f.debug_struct("BDTR")
506            .field("dtg", &self.dtg())
507            .field("lock", &self.lock())
508            .field("ossi", &self.ossi())
509            .field("ossr", &self.ossr())
510            .field("bke", &self.bke())
511            .field("bkp", &self.bkp())
512            .field("aoe", &self.aoe())
513            .field("moe", &self.moe())
514            .field("bkf", &self.bkf())
515            .field("bkdsrm", &self.bkdsrm())
516            .field("bkbid", &self.bkbid())
517            .finish()
518    }
519}
520impl W {
521    ///Bits 0:7 - Dead-time generator setup
522    #[inline(always)]
523    pub fn dtg(&mut self) -> DTG_W<BDTRrs> {
524        DTG_W::new(self, 0)
525    }
526    ///Bits 8:9 - Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
527    #[inline(always)]
528    pub fn lock(&mut self) -> LOCK_W<BDTRrs> {
529        LOCK_W::new(self, 8)
530    }
531    ///Bit 10 - Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
532    #[inline(always)]
533    pub fn ossi(&mut self) -> OSSI_W<BDTRrs> {
534        OSSI_W::new(self, 10)
535    }
536    ///Bit 11 - Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
537    #[inline(always)]
538    pub fn ossr(&mut self) -> OSSR_W<BDTRrs> {
539        OSSR_W::new(self, 11)
540    }
541    ///Bit 12 - Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
542    #[inline(always)]
543    pub fn bke(&mut self) -> BKE_W<BDTRrs> {
544        BKE_W::new(self, 12)
545    }
546    ///Bit 13 - Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
547    #[inline(always)]
548    pub fn bkp(&mut self) -> BKP_W<BDTRrs> {
549        BKP_W::new(self, 13)
550    }
551    ///Bit 14 - Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
552    #[inline(always)]
553    pub fn aoe(&mut self) -> AOE_W<BDTRrs> {
554        AOE_W::new(self, 14)
555    }
556    ///Bit 15 - Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page846).
557    #[inline(always)]
558    pub fn moe(&mut self) -> MOE_W<BDTRrs> {
559        MOE_W::new(self, 15)
560    }
561    ///Bits 16:19 - Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
562    #[inline(always)]
563    pub fn bkf(&mut self) -> BKF_W<BDTRrs> {
564        BKF_W::new(self, 16)
565    }
566    ///Bit 26 - Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
567    #[inline(always)]
568    pub fn bkdsrm(&mut self) -> BKDSRM_W<BDTRrs> {
569        BKDSRM_W::new(self, 26)
570    }
571    ///Bit 28 - Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
572    #[inline(always)]
573    pub fn bkbid(&mut self) -> BKBID_W<BDTRrs> {
574        BKBID_W::new(self, 28)
575    }
576}
577/**break and dead-time register
578
579You can [`read`](crate::Reg::read) this register and get [`bdtr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
580
581See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:BDTR)*/
582pub struct BDTRrs;
583impl crate::RegisterSpec for BDTRrs {
584    type Ux = u32;
585}
586///`read()` method returns [`bdtr::R`](R) reader structure
587impl crate::Readable for BDTRrs {}
588///`write(|w| ..)` method takes [`bdtr::W`](W) writer structure
589impl crate::Writable for BDTRrs {
590    type Safety = crate::Unsafe;
591}
592///`reset()` method sets BDTR to value 0
593impl crate::Resettable for BDTRrs {}
stm32g0/stm32g0b0/tim16/bdtr.rs

stm32g0/stm32g0b0/tim16/
bdtr.rs
