stm32g0/stm32g0b0/tim15/
ccmr1_output.rs

1///Register `CCMR1_Output` reader
2pub type R = crate::R<CCMR1_OUTPUTrs>;
3///Register `CCMR1_Output` writer
4pub type W = crate::W<CCMR1_OUTPUTrs>;
5/**Capture/Compare %s selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum CC1S {
12    ///0: CCx channel is configured as output
13    Output = 0,
14}
15impl From<CC1S> for u8 {
16    #[inline(always)]
17    fn from(variant: CC1S) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for CC1S {
22    type Ux = u8;
23}
24impl crate::IsEnum for CC1S {}
25///Field `CCS(1-2)` reader - Capture/Compare %s selection
26pub type CCS_R = crate::FieldReader<CC1S>;
27impl CCS_R {
28    ///Get enumerated values variant
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<CC1S> {
31        match self.bits {
32            0 => Some(CC1S::Output),
33            _ => None,
34        }
35    }
36    ///CCx channel is configured as output
37    #[inline(always)]
38    pub fn is_output(&self) -> bool {
39        *self == CC1S::Output
40    }
41}
42///Field `CCS(1-2)` writer - Capture/Compare %s selection
43pub type CCS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CC1S>;
44impl<'a, REG> CCS_W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47    REG::Ux: From<u8>,
48{
49    ///CCx channel is configured as output
50    #[inline(always)]
51    pub fn output(self) -> &'a mut crate::W<REG> {
52        self.variant(CC1S::Output)
53    }
54}
55/**Output compare %s fast enable
56
57Value on reset: 0*/
58#[cfg_attr(feature = "defmt", derive(defmt::Format))]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum OC1FE {
61    ///0: Fast output disabled
62    Disabled = 0,
63    ///1: Fast output enabled
64    Enabled = 1,
65}
66impl From<OC1FE> for bool {
67    #[inline(always)]
68    fn from(variant: OC1FE) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `OCFE(1-2)` reader - Output compare %s fast enable
73pub type OCFE_R = crate::BitReader<OC1FE>;
74impl OCFE_R {
75    ///Get enumerated values variant
76    #[inline(always)]
77    pub const fn variant(&self) -> OC1FE {
78        match self.bits {
79            false => OC1FE::Disabled,
80            true => OC1FE::Enabled,
81        }
82    }
83    ///Fast output disabled
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == OC1FE::Disabled
87    }
88    ///Fast output enabled
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == OC1FE::Enabled
92    }
93}
94///Field `OCFE(1-2)` writer - Output compare %s fast enable
95pub type OCFE_W<'a, REG> = crate::BitWriter<'a, REG, OC1FE>;
96impl<'a, REG> OCFE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    ///Fast output disabled
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(OC1FE::Disabled)
104    }
105    ///Fast output enabled
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(OC1FE::Enabled)
109    }
110}
111/**Output compare %s preload enable
112
113Value on reset: 0*/
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum OC1PE {
117    ///0: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
118    Disabled = 0,
119    ///1: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
120    Enabled = 1,
121}
122impl From<OC1PE> for bool {
123    #[inline(always)]
124    fn from(variant: OC1PE) -> Self {
125        variant as u8 != 0
126    }
127}
128///Field `OCPE(1-2)` reader - Output compare %s preload enable
129pub type OCPE_R = crate::BitReader<OC1PE>;
130impl OCPE_R {
131    ///Get enumerated values variant
132    #[inline(always)]
133    pub const fn variant(&self) -> OC1PE {
134        match self.bits {
135            false => OC1PE::Disabled,
136            true => OC1PE::Enabled,
137        }
138    }
139    ///Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
140    #[inline(always)]
141    pub fn is_disabled(&self) -> bool {
142        *self == OC1PE::Disabled
143    }
144    ///Preload register on CCRx enabled. Preload value is loaded into active register on each update event
145    #[inline(always)]
146    pub fn is_enabled(&self) -> bool {
147        *self == OC1PE::Enabled
148    }
149}
150///Field `OCPE(1-2)` writer - Output compare %s preload enable
151pub type OCPE_W<'a, REG> = crate::BitWriter<'a, REG, OC1PE>;
152impl<'a, REG> OCPE_W<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    ///Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
157    #[inline(always)]
158    pub fn disabled(self) -> &'a mut crate::W<REG> {
159        self.variant(OC1PE::Disabled)
160    }
161    ///Preload register on CCRx enabled. Preload value is loaded into active register on each update event
162    #[inline(always)]
163    pub fn enabled(self) -> &'a mut crate::W<REG> {
164        self.variant(OC1PE::Enabled)
165    }
166}
167/**Output compare %s mode
168
169Value on reset: 0*/
170#[cfg_attr(feature = "defmt", derive(defmt::Format))]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172#[repr(u8)]
173pub enum OC1M {
174    ///0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
175    Frozen = 0,
176    ///1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
177    ActiveOnMatch = 1,
178    ///2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
179    InactiveOnMatch = 2,
180    ///3: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
181    Toggle = 3,
182    ///4: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
183    ForceInactive = 4,
184    ///5: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
185    ForceActive = 5,
186    ///6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
187    PwmMode1 = 6,
188    ///7: Inversely to PwmMode1 / Reserved
189    PwmMode2 = 7,
190}
191impl From<OC1M> for u8 {
192    #[inline(always)]
193    fn from(variant: OC1M) -> Self {
194        variant as _
195    }
196}
197impl crate::FieldSpec for OC1M {
198    type Ux = u8;
199}
200impl crate::IsEnum for OC1M {}
201///Field `OCM(1-2)` reader - Output compare %s mode
202pub type OCM_R = crate::FieldReader<OC1M>;
203impl OCM_R {
204    ///Get enumerated values variant
205    #[inline(always)]
206    pub const fn variant(&self) -> OC1M {
207        match self.bits {
208            0 => OC1M::Frozen,
209            1 => OC1M::ActiveOnMatch,
210            2 => OC1M::InactiveOnMatch,
211            3 => OC1M::Toggle,
212            4 => OC1M::ForceInactive,
213            5 => OC1M::ForceActive,
214            6 => OC1M::PwmMode1,
215            7 => OC1M::PwmMode2,
216            _ => unreachable!(),
217        }
218    }
219    ///The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
220    #[inline(always)]
221    pub fn is_frozen(&self) -> bool {
222        *self == OC1M::Frozen
223    }
224    ///Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
225    #[inline(always)]
226    pub fn is_active_on_match(&self) -> bool {
227        *self == OC1M::ActiveOnMatch
228    }
229    ///Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
230    #[inline(always)]
231    pub fn is_inactive_on_match(&self) -> bool {
232        *self == OC1M::InactiveOnMatch
233    }
234    ///OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
235    #[inline(always)]
236    pub fn is_toggle(&self) -> bool {
237        *self == OC1M::Toggle
238    }
239    ///OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
240    #[inline(always)]
241    pub fn is_force_inactive(&self) -> bool {
242        *self == OC1M::ForceInactive
243    }
244    ///OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
245    #[inline(always)]
246    pub fn is_force_active(&self) -> bool {
247        *self == OC1M::ForceActive
248    }
249    ///In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
250    #[inline(always)]
251    pub fn is_pwm_mode1(&self) -> bool {
252        *self == OC1M::PwmMode1
253    }
254    ///Inversely to PwmMode1 / Reserved
255    #[inline(always)]
256    pub fn is_pwm_mode2(&self) -> bool {
257        *self == OC1M::PwmMode2
258    }
259}
260///Field `OCM(1-2)` writer - Output compare %s mode
261pub type OCM_W<'a, REG> = crate::FieldWriter<'a, REG, 3, OC1M, crate::Safe>;
262impl<'a, REG> OCM_W<'a, REG>
263where
264    REG: crate::Writable + crate::RegisterSpec,
265    REG::Ux: From<u8>,
266{
267    ///The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
268    #[inline(always)]
269    pub fn frozen(self) -> &'a mut crate::W<REG> {
270        self.variant(OC1M::Frozen)
271    }
272    ///Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
273    #[inline(always)]
274    pub fn active_on_match(self) -> &'a mut crate::W<REG> {
275        self.variant(OC1M::ActiveOnMatch)
276    }
277    ///Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
278    #[inline(always)]
279    pub fn inactive_on_match(self) -> &'a mut crate::W<REG> {
280        self.variant(OC1M::InactiveOnMatch)
281    }
282    ///OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
283    #[inline(always)]
284    pub fn toggle(self) -> &'a mut crate::W<REG> {
285        self.variant(OC1M::Toggle)
286    }
287    ///OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
288    #[inline(always)]
289    pub fn force_inactive(self) -> &'a mut crate::W<REG> {
290        self.variant(OC1M::ForceInactive)
291    }
292    ///OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
293    #[inline(always)]
294    pub fn force_active(self) -> &'a mut crate::W<REG> {
295        self.variant(OC1M::ForceActive)
296    }
297    ///In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
298    #[inline(always)]
299    pub fn pwm_mode1(self) -> &'a mut crate::W<REG> {
300        self.variant(OC1M::PwmMode1)
301    }
302    ///Inversely to PwmMode1 / Reserved
303    #[inline(always)]
304    pub fn pwm_mode2(self) -> &'a mut crate::W<REG> {
305        self.variant(OC1M::PwmMode2)
306    }
307}
308/**Output compare %s mode, bit 3
309
310Value on reset: 0*/
311#[cfg_attr(feature = "defmt", derive(defmt::Format))]
312#[derive(Clone, Copy, Debug, PartialEq, Eq)]
313pub enum OC1M_3 {
314    ///0: Normal output compare mode (modes 0-7)
315    Normal = 0,
316    ///1: Extended output compare mode (modes 7-15)
317    Extended = 1,
318}
319impl From<OC1M_3> for bool {
320    #[inline(always)]
321    fn from(variant: OC1M_3) -> Self {
322        variant as u8 != 0
323    }
324}
325///Field `OCM_3(1-2)` reader - Output compare %s mode, bit 3
326pub type OCM_3_R = crate::BitReader<OC1M_3>;
327impl OCM_3_R {
328    ///Get enumerated values variant
329    #[inline(always)]
330    pub const fn variant(&self) -> OC1M_3 {
331        match self.bits {
332            false => OC1M_3::Normal,
333            true => OC1M_3::Extended,
334        }
335    }
336    ///Normal output compare mode (modes 0-7)
337    #[inline(always)]
338    pub fn is_normal(&self) -> bool {
339        *self == OC1M_3::Normal
340    }
341    ///Extended output compare mode (modes 7-15)
342    #[inline(always)]
343    pub fn is_extended(&self) -> bool {
344        *self == OC1M_3::Extended
345    }
346}
347///Field `OCM_3(1-2)` writer - Output compare %s mode, bit 3
348pub type OCM_3_W<'a, REG> = crate::BitWriter<'a, REG, OC1M_3>;
349impl<'a, REG> OCM_3_W<'a, REG>
350where
351    REG: crate::Writable + crate::RegisterSpec,
352{
353    ///Normal output compare mode (modes 0-7)
354    #[inline(always)]
355    pub fn normal(self) -> &'a mut crate::W<REG> {
356        self.variant(OC1M_3::Normal)
357    }
358    ///Extended output compare mode (modes 7-15)
359    #[inline(always)]
360    pub fn extended(self) -> &'a mut crate::W<REG> {
361        self.variant(OC1M_3::Extended)
362    }
363}
364impl R {
365    ///Capture/Compare (1-2) selection
366    ///
367    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1S` field.</div>
368    #[inline(always)]
369    pub fn ccs(&self, n: u8) -> CCS_R {
370        #[allow(clippy::no_effect)]
371        [(); 2][n as usize];
372        CCS_R::new(((self.bits >> (n * 8)) & 3) as u8)
373    }
374    ///Iterator for array of:
375    ///Capture/Compare (1-2) selection
376    #[inline(always)]
377    pub fn ccs_iter(&self) -> impl Iterator<Item = CCS_R> + '_ {
378        (0..2).map(move |n| CCS_R::new(((self.bits >> (n * 8)) & 3) as u8))
379    }
380    ///Bits 0:1 - Capture/Compare 1 selection
381    #[inline(always)]
382    pub fn cc1s(&self) -> CCS_R {
383        CCS_R::new((self.bits & 3) as u8)
384    }
385    ///Bits 8:9 - Capture/Compare 2 selection
386    #[inline(always)]
387    pub fn cc2s(&self) -> CCS_R {
388        CCS_R::new(((self.bits >> 8) & 3) as u8)
389    }
390    ///Output compare (1-2) fast enable
391    ///
392    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1FE` field.</div>
393    #[inline(always)]
394    pub fn ocfe(&self, n: u8) -> OCFE_R {
395        #[allow(clippy::no_effect)]
396        [(); 2][n as usize];
397        OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0)
398    }
399    ///Iterator for array of:
400    ///Output compare (1-2) fast enable
401    #[inline(always)]
402    pub fn ocfe_iter(&self) -> impl Iterator<Item = OCFE_R> + '_ {
403        (0..2).map(move |n| OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0))
404    }
405    ///Bit 2 - Output compare 1 fast enable
406    #[inline(always)]
407    pub fn oc1fe(&self) -> OCFE_R {
408        OCFE_R::new(((self.bits >> 2) & 1) != 0)
409    }
410    ///Bit 10 - Output compare 2 fast enable
411    #[inline(always)]
412    pub fn oc2fe(&self) -> OCFE_R {
413        OCFE_R::new(((self.bits >> 10) & 1) != 0)
414    }
415    ///Output compare (1-2) preload enable
416    ///
417    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1PE` field.</div>
418    #[inline(always)]
419    pub fn ocpe(&self, n: u8) -> OCPE_R {
420        #[allow(clippy::no_effect)]
421        [(); 2][n as usize];
422        OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0)
423    }
424    ///Iterator for array of:
425    ///Output compare (1-2) preload enable
426    #[inline(always)]
427    pub fn ocpe_iter(&self) -> impl Iterator<Item = OCPE_R> + '_ {
428        (0..2).map(move |n| OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0))
429    }
430    ///Bit 3 - Output compare 1 preload enable
431    #[inline(always)]
432    pub fn oc1pe(&self) -> OCPE_R {
433        OCPE_R::new(((self.bits >> 3) & 1) != 0)
434    }
435    ///Bit 11 - Output compare 2 preload enable
436    #[inline(always)]
437    pub fn oc2pe(&self) -> OCPE_R {
438        OCPE_R::new(((self.bits >> 11) & 1) != 0)
439    }
440    ///Output compare (1-2) mode
441    ///
442    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M` field.</div>
443    #[inline(always)]
444    pub fn ocm(&self, n: u8) -> OCM_R {
445        #[allow(clippy::no_effect)]
446        [(); 2][n as usize];
447        OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8)
448    }
449    ///Iterator for array of:
450    ///Output compare (1-2) mode
451    #[inline(always)]
452    pub fn ocm_iter(&self) -> impl Iterator<Item = OCM_R> + '_ {
453        (0..2).map(move |n| OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8))
454    }
455    ///Bits 4:6 - Output compare 1 mode
456    #[inline(always)]
457    pub fn oc1m(&self) -> OCM_R {
458        OCM_R::new(((self.bits >> 4) & 7) as u8)
459    }
460    ///Bits 12:14 - Output compare 2 mode
461    #[inline(always)]
462    pub fn oc2m(&self) -> OCM_R {
463        OCM_R::new(((self.bits >> 12) & 7) as u8)
464    }
465    ///Output compare (1-2) mode, bit 3
466    ///
467    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M_3` field.</div>
468    #[inline(always)]
469    pub fn ocm_3(&self, n: u8) -> OCM_3_R {
470        #[allow(clippy::no_effect)]
471        [(); 2][n as usize];
472        OCM_3_R::new(((self.bits >> (n * 8 + 16)) & 1) != 0)
473    }
474    ///Iterator for array of:
475    ///Output compare (1-2) mode, bit 3
476    #[inline(always)]
477    pub fn ocm_3_iter(&self) -> impl Iterator<Item = OCM_3_R> + '_ {
478        (0..2).map(move |n| OCM_3_R::new(((self.bits >> (n * 8 + 16)) & 1) != 0))
479    }
480    ///Bit 16 - Output compare 1 mode, bit 3
481    #[inline(always)]
482    pub fn oc1m_3(&self) -> OCM_3_R {
483        OCM_3_R::new(((self.bits >> 16) & 1) != 0)
484    }
485    ///Bit 24 - Output compare 2 mode, bit 3
486    #[inline(always)]
487    pub fn oc2m_3(&self) -> OCM_3_R {
488        OCM_3_R::new(((self.bits >> 24) & 1) != 0)
489    }
490}
491impl core::fmt::Debug for R {
492    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
493        f.debug_struct("CCMR1_Output")
494            .field("cc1s", &self.cc1s())
495            .field("cc2s", &self.cc2s())
496            .field("oc1fe", &self.oc1fe())
497            .field("oc2fe", &self.oc2fe())
498            .field("oc1pe", &self.oc1pe())
499            .field("oc2pe", &self.oc2pe())
500            .field("oc1m", &self.oc1m())
501            .field("oc2m", &self.oc2m())
502            .field("oc1m_3", &self.oc1m_3())
503            .field("oc2m_3", &self.oc2m_3())
504            .finish()
505    }
506}
507impl W {
508    ///Capture/Compare (1-2) selection
509    ///
510    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1S` field.</div>
511    #[inline(always)]
512    pub fn ccs(&mut self, n: u8) -> CCS_W<CCMR1_OUTPUTrs> {
513        #[allow(clippy::no_effect)]
514        [(); 2][n as usize];
515        CCS_W::new(self, n * 8)
516    }
517    ///Bits 0:1 - Capture/Compare 1 selection
518    #[inline(always)]
519    pub fn cc1s(&mut self) -> CCS_W<CCMR1_OUTPUTrs> {
520        CCS_W::new(self, 0)
521    }
522    ///Bits 8:9 - Capture/Compare 2 selection
523    #[inline(always)]
524    pub fn cc2s(&mut self) -> CCS_W<CCMR1_OUTPUTrs> {
525        CCS_W::new(self, 8)
526    }
527    ///Output compare (1-2) fast enable
528    ///
529    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1FE` field.</div>
530    #[inline(always)]
531    pub fn ocfe(&mut self, n: u8) -> OCFE_W<CCMR1_OUTPUTrs> {
532        #[allow(clippy::no_effect)]
533        [(); 2][n as usize];
534        OCFE_W::new(self, n * 8 + 2)
535    }
536    ///Bit 2 - Output compare 1 fast enable
537    #[inline(always)]
538    pub fn oc1fe(&mut self) -> OCFE_W<CCMR1_OUTPUTrs> {
539        OCFE_W::new(self, 2)
540    }
541    ///Bit 10 - Output compare 2 fast enable
542    #[inline(always)]
543    pub fn oc2fe(&mut self) -> OCFE_W<CCMR1_OUTPUTrs> {
544        OCFE_W::new(self, 10)
545    }
546    ///Output compare (1-2) preload enable
547    ///
548    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1PE` field.</div>
549    #[inline(always)]
550    pub fn ocpe(&mut self, n: u8) -> OCPE_W<CCMR1_OUTPUTrs> {
551        #[allow(clippy::no_effect)]
552        [(); 2][n as usize];
553        OCPE_W::new(self, n * 8 + 3)
554    }
555    ///Bit 3 - Output compare 1 preload enable
556    #[inline(always)]
557    pub fn oc1pe(&mut self) -> OCPE_W<CCMR1_OUTPUTrs> {
558        OCPE_W::new(self, 3)
559    }
560    ///Bit 11 - Output compare 2 preload enable
561    #[inline(always)]
562    pub fn oc2pe(&mut self) -> OCPE_W<CCMR1_OUTPUTrs> {
563        OCPE_W::new(self, 11)
564    }
565    ///Output compare (1-2) mode
566    ///
567    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M` field.</div>
568    #[inline(always)]
569    pub fn ocm(&mut self, n: u8) -> OCM_W<CCMR1_OUTPUTrs> {
570        #[allow(clippy::no_effect)]
571        [(); 2][n as usize];
572        OCM_W::new(self, n * 8 + 4)
573    }
574    ///Bits 4:6 - Output compare 1 mode
575    #[inline(always)]
576    pub fn oc1m(&mut self) -> OCM_W<CCMR1_OUTPUTrs> {
577        OCM_W::new(self, 4)
578    }
579    ///Bits 12:14 - Output compare 2 mode
580    #[inline(always)]
581    pub fn oc2m(&mut self) -> OCM_W<CCMR1_OUTPUTrs> {
582        OCM_W::new(self, 12)
583    }
584    ///Output compare (1-2) mode, bit 3
585    ///
586    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M_3` field.</div>
587    #[inline(always)]
588    pub fn ocm_3(&mut self, n: u8) -> OCM_3_W<CCMR1_OUTPUTrs> {
589        #[allow(clippy::no_effect)]
590        [(); 2][n as usize];
591        OCM_3_W::new(self, n * 8 + 16)
592    }
593    ///Bit 16 - Output compare 1 mode, bit 3
594    #[inline(always)]
595    pub fn oc1m_3(&mut self) -> OCM_3_W<CCMR1_OUTPUTrs> {
596        OCM_3_W::new(self, 16)
597    }
598    ///Bit 24 - Output compare 2 mode, bit 3
599    #[inline(always)]
600    pub fn oc2m_3(&mut self) -> OCM_3_W<CCMR1_OUTPUTrs> {
601        OCM_3_W::new(self, 24)
602    }
603}
604/**capture/compare mode register (output mode)
605
606You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
607
608See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:CCMR1_Output)*/
609pub struct CCMR1_OUTPUTrs;
610impl crate::RegisterSpec for CCMR1_OUTPUTrs {
611    type Ux = u32;
612}
613///`read()` method returns [`ccmr1_output::R`](R) reader structure
614impl crate::Readable for CCMR1_OUTPUTrs {}
615///`write(|w| ..)` method takes [`ccmr1_output::W`](W) writer structure
616impl crate::Writable for CCMR1_OUTPUTrs {
617    type Safety = crate::Unsafe;
618}
619///`reset()` method sets CCMR1_Output to value 0
620impl crate::Resettable for CCMR1_OUTPUTrs {}
stm32g0/stm32g0b0/tim15/ccmr1_output.rs

stm32g0/stm32g0b0/tim15/
ccmr1_output.rs
