1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
#[doc = "Register `CCMR1_Output` reader"]
pub struct R(crate::R<CCMR1_OUTPUT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CCMR1_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CCMR1_OUTPUT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CCMR1_OUTPUT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CCMR1_Output` writer"]
pub struct W(crate::W<CCMR1_OUTPUT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CCMR1_OUTPUT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CCMR1_OUTPUT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CCMR1_OUTPUT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CC1S` reader - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â\u{80}\u{99} in TIMx_CCER)."]
pub type CC1S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC1S` writer - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â\u{80}\u{99} in TIMx_CCER)."]
pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC1FE` reader - Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger."]
pub type OC1FE_R = crate::BitReader<bool>;
#[doc = "Field `OC1FE` writer - Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger."]
pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC1PE` reader - Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed."]
pub type OC1PE_R = crate::BitReader<bool>;
#[doc = "Field `OC1PE` writer - Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed."]
pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC1M1` reader - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from â\u{80}\u{9c}frozenâ\u{80}\u{9d} mode to â\u{80}\u{9c}PWMâ\u{80}\u{9d} mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M\\[3\\]
bit is not contiguous, located in bit 16."]
pub type OC1M1_R = crate::FieldReader<u8, u8>;
#[doc = "Field `OC1M1` writer - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from â\u{80}\u{9c}frozenâ\u{80}\u{9d} mode to â\u{80}\u{9c}PWMâ\u{80}\u{9d} mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M\\[3\\]
bit is not contiguous, located in bit 16."]
pub type OC1M1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 3, O>;
#[doc = "Field `CC2S` reader - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â\u{80}\u{99} in TIMx_CCER)."]
pub type CC2S_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CC2S` writer - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â\u{80}\u{99} in TIMx_CCER)."]
pub type CC2S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, u8, 2, O>;
#[doc = "Field `OC2FE` reader - Output Compare 2 fast enable"]
pub type OC2FE_R = crate::BitReader<bool>;
#[doc = "Field `OC2FE` writer - Output Compare 2 fast enable"]
pub type OC2FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Field `OC2PE` reader - Output Compare 2 preload enable"]
pub type OC2PE_R = crate::BitReader<bool>;
#[doc = "Field `OC2PE` writer - Output Compare 2 preload enable"]
pub type OC2PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Output Compare 2 mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum OC2M_A {
#[doc = "0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
Frozen = 0,
#[doc = "1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1"]
ActiveOnMatch = 1,
#[doc = "2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved"]
InactiveOnMatch = 2,
#[doc = "3: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"]
Toggle = 3,
#[doc = "4: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
ForceInactive = 4,
#[doc = "5: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
ForceActive = 5,
#[doc = "6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved"]
PwmMode1 = 6,
#[doc = "7: Inversely to PwmMode1 / Reserved"]
PwmMode2 = 7,
}
impl From<OC2M_A> for u8 {
#[inline(always)]
fn from(variant: OC2M_A) -> Self {
variant as _
}
}
#[doc = "Field `OC2M` reader - Output Compare 2 mode"]
pub type OC2M_R = crate::FieldReader<u8, OC2M_A>;
impl OC2M_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> OC2M_A {
match self.bits {
0 => OC2M_A::Frozen,
1 => OC2M_A::ActiveOnMatch,
2 => OC2M_A::InactiveOnMatch,
3 => OC2M_A::Toggle,
4 => OC2M_A::ForceInactive,
5 => OC2M_A::ForceActive,
6 => OC2M_A::PwmMode1,
7 => OC2M_A::PwmMode2,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `Frozen`"]
#[inline(always)]
pub fn is_frozen(&self) -> bool {
*self == OC2M_A::Frozen
}
#[doc = "Checks if the value of the field is `ActiveOnMatch`"]
#[inline(always)]
pub fn is_active_on_match(&self) -> bool {
*self == OC2M_A::ActiveOnMatch
}
#[doc = "Checks if the value of the field is `InactiveOnMatch`"]
#[inline(always)]
pub fn is_inactive_on_match(&self) -> bool {
*self == OC2M_A::InactiveOnMatch
}
#[doc = "Checks if the value of the field is `Toggle`"]
#[inline(always)]
pub fn is_toggle(&self) -> bool {
*self == OC2M_A::Toggle
}
#[doc = "Checks if the value of the field is `ForceInactive`"]
#[inline(always)]
pub fn is_force_inactive(&self) -> bool {
*self == OC2M_A::ForceInactive
}
#[doc = "Checks if the value of the field is `ForceActive`"]
#[inline(always)]
pub fn is_force_active(&self) -> bool {
*self == OC2M_A::ForceActive
}
#[doc = "Checks if the value of the field is `PwmMode1`"]
#[inline(always)]
pub fn is_pwm_mode1(&self) -> bool {
*self == OC2M_A::PwmMode1
}
#[doc = "Checks if the value of the field is `PwmMode2`"]
#[inline(always)]
pub fn is_pwm_mode2(&self) -> bool {
*self == OC2M_A::PwmMode2
}
}
#[doc = "Field `OC2M` writer - Output Compare 2 mode"]
pub type OC2M_W<'a, const O: u8> =
crate::FieldWriterSafe<'a, u32, CCMR1_OUTPUT_SPEC, u8, OC2M_A, 3, O>;
impl<'a, const O: u8> OC2M_W<'a, O> {
#[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"]
#[inline(always)]
pub fn frozen(self) -> &'a mut W {
self.variant(OC2M_A::Frozen)
}
#[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1"]
#[inline(always)]
pub fn active_on_match(self) -> &'a mut W {
self.variant(OC2M_A::ActiveOnMatch)
}
#[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved"]
#[inline(always)]
pub fn inactive_on_match(self) -> &'a mut W {
self.variant(OC2M_A::InactiveOnMatch)
}
#[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"]
#[inline(always)]
pub fn toggle(self) -> &'a mut W {
self.variant(OC2M_A::Toggle)
}
#[doc = "OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"]
#[inline(always)]
pub fn force_inactive(self) -> &'a mut W {
self.variant(OC2M_A::ForceInactive)
}
#[doc = "OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"]
#[inline(always)]
pub fn force_active(self) -> &'a mut W {
self.variant(OC2M_A::ForceActive)
}
#[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved"]
#[inline(always)]
pub fn pwm_mode1(self) -> &'a mut W {
self.variant(OC2M_A::PwmMode1)
}
#[doc = "Inversely to PwmMode1 / Reserved"]
#[inline(always)]
pub fn pwm_mode2(self) -> &'a mut W {
self.variant(OC2M_A::PwmMode2)
}
}
#[doc = "Field `OC1M2` reader - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from â\u{80}\u{9c}frozenâ\u{80}\u{9d} mode to â\u{80}\u{9c}PWMâ\u{80}\u{9d} mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M\\[3\\]
bit is not contiguous, located in bit 16."]
pub type OC1M2_R = crate::BitReader<bool>;
#[doc = "Field `OC1M2` writer - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from â\u{80}\u{9c}frozenâ\u{80}\u{9d} mode to â\u{80}\u{9c}PWMâ\u{80}\u{9d} mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M\\[3\\]
bit is not contiguous, located in bit 16."]
pub type OC1M2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
#[doc = "Output Compare 2 mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OC2M_3_A {
#[doc = "0: Normal output compare mode (modes 0-7)"]
Normal = 0,
#[doc = "1: Extended output compare mode (modes 7-15)"]
Extended = 1,
}
impl From<OC2M_3_A> for bool {
#[inline(always)]
fn from(variant: OC2M_3_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OC2M_3` reader - Output Compare 2 mode"]
pub type OC2M_3_R = crate::BitReader<OC2M_3_A>;
impl OC2M_3_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> OC2M_3_A {
match self.bits {
false => OC2M_3_A::Normal,
true => OC2M_3_A::Extended,
}
}
#[doc = "Checks if the value of the field is `Normal`"]
#[inline(always)]
pub fn is_normal(&self) -> bool {
*self == OC2M_3_A::Normal
}
#[doc = "Checks if the value of the field is `Extended`"]
#[inline(always)]
pub fn is_extended(&self) -> bool {
*self == OC2M_3_A::Extended
}
}
#[doc = "Field `OC2M_3` writer - Output Compare 2 mode"]
pub type OC2M_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, OC2M_3_A, O>;
impl<'a, const O: u8> OC2M_3_W<'a, O> {
#[doc = "Normal output compare mode (modes 0-7)"]
#[inline(always)]
pub fn normal(self) -> &'a mut W {
self.variant(OC2M_3_A::Normal)
}
#[doc = "Extended output compare mode (modes 7-15)"]
#[inline(always)]
pub fn extended(self) -> &'a mut W {
self.variant(OC2M_3_A::Extended)
}
}
impl R {
#[doc = "Bits 0:1 - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â\u{80}\u{99} in TIMx_CCER)."]
#[inline(always)]
pub fn cc1s(&self) -> CC1S_R {
CC1S_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger."]
#[inline(always)]
pub fn oc1fe(&self) -> OC1FE_R {
OC1FE_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed."]
#[inline(always)]
pub fn oc1pe(&self) -> OC1PE_R {
OC1PE_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:6 - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from â\u{80}\u{9c}frozenâ\u{80}\u{9d} mode to â\u{80}\u{9c}PWMâ\u{80}\u{9d} mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M\\[3\\]
bit is not contiguous, located in bit 16."]
#[inline(always)]
pub fn oc1m1(&self) -> OC1M1_R {
OC1M1_R::new(((self.bits >> 4) & 7) as u8)
}
#[doc = "Bits 8:9 - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â\u{80}\u{99} in TIMx_CCER)."]
#[inline(always)]
pub fn cc2s(&self) -> CC2S_R {
CC2S_R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bit 10 - Output Compare 2 fast enable"]
#[inline(always)]
pub fn oc2fe(&self) -> OC2FE_R {
OC2FE_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Output Compare 2 preload enable"]
#[inline(always)]
pub fn oc2pe(&self) -> OC2PE_R {
OC2PE_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Bits 12:14 - Output Compare 2 mode"]
#[inline(always)]
pub fn oc2m(&self) -> OC2M_R {
OC2M_R::new(((self.bits >> 12) & 7) as u8)
}
#[doc = "Bit 16 - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from â\u{80}\u{9c}frozenâ\u{80}\u{9d} mode to â\u{80}\u{9c}PWMâ\u{80}\u{9d} mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M\\[3\\]
bit is not contiguous, located in bit 16."]
#[inline(always)]
pub fn oc1m2(&self) -> OC1M2_R {
OC1M2_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 24 - Output Compare 2 mode"]
#[inline(always)]
pub fn oc2m_3(&self) -> OC2M_3_R {
OC2M_3_R::new(((self.bits >> 24) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â\u{80}\u{99} in TIMx_CCER)."]
#[inline(always)]
pub fn cc1s(&mut self) -> CC1S_W<0> {
CC1S_W::new(self)
}
#[doc = "Bit 2 - Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger."]
#[inline(always)]
pub fn oc1fe(&mut self) -> OC1FE_W<2> {
OC1FE_W::new(self)
}
#[doc = "Bit 3 - Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed."]
#[inline(always)]
pub fn oc1pe(&mut self) -> OC1PE_W<3> {
OC1PE_W::new(self)
}
#[doc = "Bits 4:6 - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from â\u{80}\u{9c}frozenâ\u{80}\u{9d} mode to â\u{80}\u{9c}PWMâ\u{80}\u{9d} mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M\\[3\\]
bit is not contiguous, located in bit 16."]
#[inline(always)]
pub fn oc1m1(&mut self) -> OC1M1_W<4> {
OC1M1_W::new(self)
}
#[doc = "Bits 8:9 - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â\u{80}\u{99} in TIMx_CCER)."]
#[inline(always)]
pub fn cc2s(&mut self) -> CC2S_W<8> {
CC2S_W::new(self)
}
#[doc = "Bit 10 - Output Compare 2 fast enable"]
#[inline(always)]
pub fn oc2fe(&mut self) -> OC2FE_W<10> {
OC2FE_W::new(self)
}
#[doc = "Bit 11 - Output Compare 2 preload enable"]
#[inline(always)]
pub fn oc2pe(&mut self) -> OC2PE_W<11> {
OC2PE_W::new(self)
}
#[doc = "Bits 12:14 - Output Compare 2 mode"]
#[inline(always)]
pub fn oc2m(&mut self) -> OC2M_W<12> {
OC2M_W::new(self)
}
#[doc = "Bit 16 - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â\u{80}\u{99}00â\u{80}\u{99} (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from â\u{80}\u{9c}frozenâ\u{80}\u{9d} mode to â\u{80}\u{9c}PWMâ\u{80}\u{9d} mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M\\[3\\]
bit is not contiguous, located in bit 16."]
#[inline(always)]
pub fn oc1m2(&mut self) -> OC1M2_W<16> {
OC1M2_W::new(self)
}
#[doc = "Bit 24 - Output Compare 2 mode"]
#[inline(always)]
pub fn oc2m_3(&mut self) -> OC2M_3_W<24> {
OC2M_3_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "capture/compare mode register (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"]
pub struct CCMR1_OUTPUT_SPEC;
impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"]
impl crate::Readable for CCMR1_OUTPUT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"]
impl crate::Writable for CCMR1_OUTPUT_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CCMR1_Output to value 0"]
impl crate::Resettable for CCMR1_OUTPUT_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}
