stm32g0/stm32g081/spi1/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5/**Clock phase
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CPHA {
11    ///0: The first clock transition is the first data capture edge
12    FirstEdge = 0,
13    ///1: The second clock transition is the first data capture edge
14    SecondEdge = 1,
15}
16impl From<CPHA> for bool {
17    #[inline(always)]
18    fn from(variant: CPHA) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CPHA` reader - Clock phase
23pub type CPHA_R = crate::BitReader<CPHA>;
24impl CPHA_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CPHA {
28        match self.bits {
29            false => CPHA::FirstEdge,
30            true => CPHA::SecondEdge,
31        }
32    }
33    ///The first clock transition is the first data capture edge
34    #[inline(always)]
35    pub fn is_first_edge(&self) -> bool {
36        *self == CPHA::FirstEdge
37    }
38    ///The second clock transition is the first data capture edge
39    #[inline(always)]
40    pub fn is_second_edge(&self) -> bool {
41        *self == CPHA::SecondEdge
42    }
43}
44///Field `CPHA` writer - Clock phase
45pub type CPHA_W<'a, REG> = crate::BitWriter<'a, REG, CPHA>;
46impl<'a, REG> CPHA_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The first clock transition is the first data capture edge
51    #[inline(always)]
52    pub fn first_edge(self) -> &'a mut crate::W<REG> {
53        self.variant(CPHA::FirstEdge)
54    }
55    ///The second clock transition is the first data capture edge
56    #[inline(always)]
57    pub fn second_edge(self) -> &'a mut crate::W<REG> {
58        self.variant(CPHA::SecondEdge)
59    }
60}
61/**Clock polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CPOL {
67    ///0: CK to 0 when idle
68    IdleLow = 0,
69    ///1: CK to 1 when idle
70    IdleHigh = 1,
71}
72impl From<CPOL> for bool {
73    #[inline(always)]
74    fn from(variant: CPOL) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CPOL` reader - Clock polarity
79pub type CPOL_R = crate::BitReader<CPOL>;
80impl CPOL_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CPOL {
84        match self.bits {
85            false => CPOL::IdleLow,
86            true => CPOL::IdleHigh,
87        }
88    }
89    ///CK to 0 when idle
90    #[inline(always)]
91    pub fn is_idle_low(&self) -> bool {
92        *self == CPOL::IdleLow
93    }
94    ///CK to 1 when idle
95    #[inline(always)]
96    pub fn is_idle_high(&self) -> bool {
97        *self == CPOL::IdleHigh
98    }
99}
100///Field `CPOL` writer - Clock polarity
101pub type CPOL_W<'a, REG> = crate::BitWriter<'a, REG, CPOL>;
102impl<'a, REG> CPOL_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///CK to 0 when idle
107    #[inline(always)]
108    pub fn idle_low(self) -> &'a mut crate::W<REG> {
109        self.variant(CPOL::IdleLow)
110    }
111    ///CK to 1 when idle
112    #[inline(always)]
113    pub fn idle_high(self) -> &'a mut crate::W<REG> {
114        self.variant(CPOL::IdleHigh)
115    }
116}
117/**Master selection
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum MSTR {
123    ///0: Slave configuration
124    Slave = 0,
125    ///1: Master configuration
126    Master = 1,
127}
128impl From<MSTR> for bool {
129    #[inline(always)]
130    fn from(variant: MSTR) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `MSTR` reader - Master selection
135pub type MSTR_R = crate::BitReader<MSTR>;
136impl MSTR_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> MSTR {
140        match self.bits {
141            false => MSTR::Slave,
142            true => MSTR::Master,
143        }
144    }
145    ///Slave configuration
146    #[inline(always)]
147    pub fn is_slave(&self) -> bool {
148        *self == MSTR::Slave
149    }
150    ///Master configuration
151    #[inline(always)]
152    pub fn is_master(&self) -> bool {
153        *self == MSTR::Master
154    }
155}
156///Field `MSTR` writer - Master selection
157pub type MSTR_W<'a, REG> = crate::BitWriter<'a, REG, MSTR>;
158impl<'a, REG> MSTR_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Slave configuration
163    #[inline(always)]
164    pub fn slave(self) -> &'a mut crate::W<REG> {
165        self.variant(MSTR::Slave)
166    }
167    ///Master configuration
168    #[inline(always)]
169    pub fn master(self) -> &'a mut crate::W<REG> {
170        self.variant(MSTR::Master)
171    }
172}
173/**Baud rate control
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178#[repr(u8)]
179pub enum BR {
180    ///0: f_PCLK / 2
181    Div2 = 0,
182    ///1: f_PCLK / 4
183    Div4 = 1,
184    ///2: f_PCLK / 8
185    Div8 = 2,
186    ///3: f_PCLK / 16
187    Div16 = 3,
188    ///4: f_PCLK / 32
189    Div32 = 4,
190    ///5: f_PCLK / 64
191    Div64 = 5,
192    ///6: f_PCLK / 128
193    Div128 = 6,
194    ///7: f_PCLK / 256
195    Div256 = 7,
196}
197impl From<BR> for u8 {
198    #[inline(always)]
199    fn from(variant: BR) -> Self {
200        variant as _
201    }
202}
203impl crate::FieldSpec for BR {
204    type Ux = u8;
205}
206impl crate::IsEnum for BR {}
207///Field `BR` reader - Baud rate control
208pub type BR_R = crate::FieldReader<BR>;
209impl BR_R {
210    ///Get enumerated values variant
211    #[inline(always)]
212    pub const fn variant(&self) -> BR {
213        match self.bits {
214            0 => BR::Div2,
215            1 => BR::Div4,
216            2 => BR::Div8,
217            3 => BR::Div16,
218            4 => BR::Div32,
219            5 => BR::Div64,
220            6 => BR::Div128,
221            7 => BR::Div256,
222            _ => unreachable!(),
223        }
224    }
225    ///f_PCLK / 2
226    #[inline(always)]
227    pub fn is_div2(&self) -> bool {
228        *self == BR::Div2
229    }
230    ///f_PCLK / 4
231    #[inline(always)]
232    pub fn is_div4(&self) -> bool {
233        *self == BR::Div4
234    }
235    ///f_PCLK / 8
236    #[inline(always)]
237    pub fn is_div8(&self) -> bool {
238        *self == BR::Div8
239    }
240    ///f_PCLK / 16
241    #[inline(always)]
242    pub fn is_div16(&self) -> bool {
243        *self == BR::Div16
244    }
245    ///f_PCLK / 32
246    #[inline(always)]
247    pub fn is_div32(&self) -> bool {
248        *self == BR::Div32
249    }
250    ///f_PCLK / 64
251    #[inline(always)]
252    pub fn is_div64(&self) -> bool {
253        *self == BR::Div64
254    }
255    ///f_PCLK / 128
256    #[inline(always)]
257    pub fn is_div128(&self) -> bool {
258        *self == BR::Div128
259    }
260    ///f_PCLK / 256
261    #[inline(always)]
262    pub fn is_div256(&self) -> bool {
263        *self == BR::Div256
264    }
265}
266///Field `BR` writer - Baud rate control
267pub type BR_W<'a, REG> = crate::FieldWriter<'a, REG, 3, BR, crate::Safe>;
268impl<'a, REG> BR_W<'a, REG>
269where
270    REG: crate::Writable + crate::RegisterSpec,
271    REG::Ux: From<u8>,
272{
273    ///f_PCLK / 2
274    #[inline(always)]
275    pub fn div2(self) -> &'a mut crate::W<REG> {
276        self.variant(BR::Div2)
277    }
278    ///f_PCLK / 4
279    #[inline(always)]
280    pub fn div4(self) -> &'a mut crate::W<REG> {
281        self.variant(BR::Div4)
282    }
283    ///f_PCLK / 8
284    #[inline(always)]
285    pub fn div8(self) -> &'a mut crate::W<REG> {
286        self.variant(BR::Div8)
287    }
288    ///f_PCLK / 16
289    #[inline(always)]
290    pub fn div16(self) -> &'a mut crate::W<REG> {
291        self.variant(BR::Div16)
292    }
293    ///f_PCLK / 32
294    #[inline(always)]
295    pub fn div32(self) -> &'a mut crate::W<REG> {
296        self.variant(BR::Div32)
297    }
298    ///f_PCLK / 64
299    #[inline(always)]
300    pub fn div64(self) -> &'a mut crate::W<REG> {
301        self.variant(BR::Div64)
302    }
303    ///f_PCLK / 128
304    #[inline(always)]
305    pub fn div128(self) -> &'a mut crate::W<REG> {
306        self.variant(BR::Div128)
307    }
308    ///f_PCLK / 256
309    #[inline(always)]
310    pub fn div256(self) -> &'a mut crate::W<REG> {
311        self.variant(BR::Div256)
312    }
313}
314/**SPI enable
315
316Value on reset: 0*/
317#[cfg_attr(feature = "defmt", derive(defmt::Format))]
318#[derive(Clone, Copy, Debug, PartialEq, Eq)]
319pub enum SPE {
320    ///0: Peripheral disabled
321    Disabled = 0,
322    ///1: Peripheral enabled
323    Enabled = 1,
324}
325impl From<SPE> for bool {
326    #[inline(always)]
327    fn from(variant: SPE) -> Self {
328        variant as u8 != 0
329    }
330}
331///Field `SPE` reader - SPI enable
332pub type SPE_R = crate::BitReader<SPE>;
333impl SPE_R {
334    ///Get enumerated values variant
335    #[inline(always)]
336    pub const fn variant(&self) -> SPE {
337        match self.bits {
338            false => SPE::Disabled,
339            true => SPE::Enabled,
340        }
341    }
342    ///Peripheral disabled
343    #[inline(always)]
344    pub fn is_disabled(&self) -> bool {
345        *self == SPE::Disabled
346    }
347    ///Peripheral enabled
348    #[inline(always)]
349    pub fn is_enabled(&self) -> bool {
350        *self == SPE::Enabled
351    }
352}
353///Field `SPE` writer - SPI enable
354pub type SPE_W<'a, REG> = crate::BitWriter<'a, REG, SPE>;
355impl<'a, REG> SPE_W<'a, REG>
356where
357    REG: crate::Writable + crate::RegisterSpec,
358{
359    ///Peripheral disabled
360    #[inline(always)]
361    pub fn disabled(self) -> &'a mut crate::W<REG> {
362        self.variant(SPE::Disabled)
363    }
364    ///Peripheral enabled
365    #[inline(always)]
366    pub fn enabled(self) -> &'a mut crate::W<REG> {
367        self.variant(SPE::Enabled)
368    }
369}
370/**Frame format
371
372Value on reset: 0*/
373#[cfg_attr(feature = "defmt", derive(defmt::Format))]
374#[derive(Clone, Copy, Debug, PartialEq, Eq)]
375pub enum LSBFIRST {
376    ///0: Data is transmitted/received with the MSB first
377    Msbfirst = 0,
378    ///1: Data is transmitted/received with the LSB first
379    Lsbfirst = 1,
380}
381impl From<LSBFIRST> for bool {
382    #[inline(always)]
383    fn from(variant: LSBFIRST) -> Self {
384        variant as u8 != 0
385    }
386}
387///Field `LSBFIRST` reader - Frame format
388pub type LSBFIRST_R = crate::BitReader<LSBFIRST>;
389impl LSBFIRST_R {
390    ///Get enumerated values variant
391    #[inline(always)]
392    pub const fn variant(&self) -> LSBFIRST {
393        match self.bits {
394            false => LSBFIRST::Msbfirst,
395            true => LSBFIRST::Lsbfirst,
396        }
397    }
398    ///Data is transmitted/received with the MSB first
399    #[inline(always)]
400    pub fn is_msbfirst(&self) -> bool {
401        *self == LSBFIRST::Msbfirst
402    }
403    ///Data is transmitted/received with the LSB first
404    #[inline(always)]
405    pub fn is_lsbfirst(&self) -> bool {
406        *self == LSBFIRST::Lsbfirst
407    }
408}
409///Field `LSBFIRST` writer - Frame format
410pub type LSBFIRST_W<'a, REG> = crate::BitWriter<'a, REG, LSBFIRST>;
411impl<'a, REG> LSBFIRST_W<'a, REG>
412where
413    REG: crate::Writable + crate::RegisterSpec,
414{
415    ///Data is transmitted/received with the MSB first
416    #[inline(always)]
417    pub fn msbfirst(self) -> &'a mut crate::W<REG> {
418        self.variant(LSBFIRST::Msbfirst)
419    }
420    ///Data is transmitted/received with the LSB first
421    #[inline(always)]
422    pub fn lsbfirst(self) -> &'a mut crate::W<REG> {
423        self.variant(LSBFIRST::Lsbfirst)
424    }
425}
426/**Internal slave select
427
428Value on reset: 0*/
429#[cfg_attr(feature = "defmt", derive(defmt::Format))]
430#[derive(Clone, Copy, Debug, PartialEq, Eq)]
431pub enum SSI {
432    ///0: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
433    SlaveSelected = 0,
434    ///1: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
435    SlaveNotSelected = 1,
436}
437impl From<SSI> for bool {
438    #[inline(always)]
439    fn from(variant: SSI) -> Self {
440        variant as u8 != 0
441    }
442}
443///Field `SSI` reader - Internal slave select
444pub type SSI_R = crate::BitReader<SSI>;
445impl SSI_R {
446    ///Get enumerated values variant
447    #[inline(always)]
448    pub const fn variant(&self) -> SSI {
449        match self.bits {
450            false => SSI::SlaveSelected,
451            true => SSI::SlaveNotSelected,
452        }
453    }
454    ///0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
455    #[inline(always)]
456    pub fn is_slave_selected(&self) -> bool {
457        *self == SSI::SlaveSelected
458    }
459    ///1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
460    #[inline(always)]
461    pub fn is_slave_not_selected(&self) -> bool {
462        *self == SSI::SlaveNotSelected
463    }
464}
465///Field `SSI` writer - Internal slave select
466pub type SSI_W<'a, REG> = crate::BitWriter<'a, REG, SSI>;
467impl<'a, REG> SSI_W<'a, REG>
468where
469    REG: crate::Writable + crate::RegisterSpec,
470{
471    ///0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
472    #[inline(always)]
473    pub fn slave_selected(self) -> &'a mut crate::W<REG> {
474        self.variant(SSI::SlaveSelected)
475    }
476    ///1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
477    #[inline(always)]
478    pub fn slave_not_selected(self) -> &'a mut crate::W<REG> {
479        self.variant(SSI::SlaveNotSelected)
480    }
481}
482/**Software slave management
483
484Value on reset: 0*/
485#[cfg_attr(feature = "defmt", derive(defmt::Format))]
486#[derive(Clone, Copy, Debug, PartialEq, Eq)]
487pub enum SSM {
488    ///0: Software slave management disabled
489    Disabled = 0,
490    ///1: Software slave management enabled
491    Enabled = 1,
492}
493impl From<SSM> for bool {
494    #[inline(always)]
495    fn from(variant: SSM) -> Self {
496        variant as u8 != 0
497    }
498}
499///Field `SSM` reader - Software slave management
500pub type SSM_R = crate::BitReader<SSM>;
501impl SSM_R {
502    ///Get enumerated values variant
503    #[inline(always)]
504    pub const fn variant(&self) -> SSM {
505        match self.bits {
506            false => SSM::Disabled,
507            true => SSM::Enabled,
508        }
509    }
510    ///Software slave management disabled
511    #[inline(always)]
512    pub fn is_disabled(&self) -> bool {
513        *self == SSM::Disabled
514    }
515    ///Software slave management enabled
516    #[inline(always)]
517    pub fn is_enabled(&self) -> bool {
518        *self == SSM::Enabled
519    }
520}
521///Field `SSM` writer - Software slave management
522pub type SSM_W<'a, REG> = crate::BitWriter<'a, REG, SSM>;
523impl<'a, REG> SSM_W<'a, REG>
524where
525    REG: crate::Writable + crate::RegisterSpec,
526{
527    ///Software slave management disabled
528    #[inline(always)]
529    pub fn disabled(self) -> &'a mut crate::W<REG> {
530        self.variant(SSM::Disabled)
531    }
532    ///Software slave management enabled
533    #[inline(always)]
534    pub fn enabled(self) -> &'a mut crate::W<REG> {
535        self.variant(SSM::Enabled)
536    }
537}
538/**Receive only
539
540Value on reset: 0*/
541#[cfg_attr(feature = "defmt", derive(defmt::Format))]
542#[derive(Clone, Copy, Debug, PartialEq, Eq)]
543pub enum RXONLY {
544    ///0: Full duplex (Transmit and receive)
545    FullDuplex = 0,
546    ///1: Output disabled (Receive-only mode)
547    OutputDisabled = 1,
548}
549impl From<RXONLY> for bool {
550    #[inline(always)]
551    fn from(variant: RXONLY) -> Self {
552        variant as u8 != 0
553    }
554}
555///Field `RXONLY` reader - Receive only
556pub type RXONLY_R = crate::BitReader<RXONLY>;
557impl RXONLY_R {
558    ///Get enumerated values variant
559    #[inline(always)]
560    pub const fn variant(&self) -> RXONLY {
561        match self.bits {
562            false => RXONLY::FullDuplex,
563            true => RXONLY::OutputDisabled,
564        }
565    }
566    ///Full duplex (Transmit and receive)
567    #[inline(always)]
568    pub fn is_full_duplex(&self) -> bool {
569        *self == RXONLY::FullDuplex
570    }
571    ///Output disabled (Receive-only mode)
572    #[inline(always)]
573    pub fn is_output_disabled(&self) -> bool {
574        *self == RXONLY::OutputDisabled
575    }
576}
577///Field `RXONLY` writer - Receive only
578pub type RXONLY_W<'a, REG> = crate::BitWriter<'a, REG, RXONLY>;
579impl<'a, REG> RXONLY_W<'a, REG>
580where
581    REG: crate::Writable + crate::RegisterSpec,
582{
583    ///Full duplex (Transmit and receive)
584    #[inline(always)]
585    pub fn full_duplex(self) -> &'a mut crate::W<REG> {
586        self.variant(RXONLY::FullDuplex)
587    }
588    ///Output disabled (Receive-only mode)
589    #[inline(always)]
590    pub fn output_disabled(self) -> &'a mut crate::W<REG> {
591        self.variant(RXONLY::OutputDisabled)
592    }
593}
594/**CRC length
595
596Value on reset: 0*/
597#[cfg_attr(feature = "defmt", derive(defmt::Format))]
598#[derive(Clone, Copy, Debug, PartialEq, Eq)]
599pub enum CRCL {
600    ///0: 8-bit CRC length
601    EightBit = 0,
602    ///1: 16-bit CRC length
603    SixteenBit = 1,
604}
605impl From<CRCL> for bool {
606    #[inline(always)]
607    fn from(variant: CRCL) -> Self {
608        variant as u8 != 0
609    }
610}
611///Field `CRCL` reader - CRC length
612pub type CRCL_R = crate::BitReader<CRCL>;
613impl CRCL_R {
614    ///Get enumerated values variant
615    #[inline(always)]
616    pub const fn variant(&self) -> CRCL {
617        match self.bits {
618            false => CRCL::EightBit,
619            true => CRCL::SixteenBit,
620        }
621    }
622    ///8-bit CRC length
623    #[inline(always)]
624    pub fn is_eight_bit(&self) -> bool {
625        *self == CRCL::EightBit
626    }
627    ///16-bit CRC length
628    #[inline(always)]
629    pub fn is_sixteen_bit(&self) -> bool {
630        *self == CRCL::SixteenBit
631    }
632}
633///Field `CRCL` writer - CRC length
634pub type CRCL_W<'a, REG> = crate::BitWriter<'a, REG, CRCL>;
635impl<'a, REG> CRCL_W<'a, REG>
636where
637    REG: crate::Writable + crate::RegisterSpec,
638{
639    ///8-bit CRC length
640    #[inline(always)]
641    pub fn eight_bit(self) -> &'a mut crate::W<REG> {
642        self.variant(CRCL::EightBit)
643    }
644    ///16-bit CRC length
645    #[inline(always)]
646    pub fn sixteen_bit(self) -> &'a mut crate::W<REG> {
647        self.variant(CRCL::SixteenBit)
648    }
649}
650/**CRC transfer next
651
652Value on reset: 0*/
653#[cfg_attr(feature = "defmt", derive(defmt::Format))]
654#[derive(Clone, Copy, Debug, PartialEq, Eq)]
655pub enum CRCNEXT {
656    ///0: Next transmit value is from Tx buffer
657    TxBuffer = 0,
658    ///1: Next transmit value is from Tx CRC register
659    Crc = 1,
660}
661impl From<CRCNEXT> for bool {
662    #[inline(always)]
663    fn from(variant: CRCNEXT) -> Self {
664        variant as u8 != 0
665    }
666}
667///Field `CRCNEXT` reader - CRC transfer next
668pub type CRCNEXT_R = crate::BitReader<CRCNEXT>;
669impl CRCNEXT_R {
670    ///Get enumerated values variant
671    #[inline(always)]
672    pub const fn variant(&self) -> CRCNEXT {
673        match self.bits {
674            false => CRCNEXT::TxBuffer,
675            true => CRCNEXT::Crc,
676        }
677    }
678    ///Next transmit value is from Tx buffer
679    #[inline(always)]
680    pub fn is_tx_buffer(&self) -> bool {
681        *self == CRCNEXT::TxBuffer
682    }
683    ///Next transmit value is from Tx CRC register
684    #[inline(always)]
685    pub fn is_crc(&self) -> bool {
686        *self == CRCNEXT::Crc
687    }
688}
689///Field `CRCNEXT` writer - CRC transfer next
690pub type CRCNEXT_W<'a, REG> = crate::BitWriter<'a, REG, CRCNEXT>;
691impl<'a, REG> CRCNEXT_W<'a, REG>
692where
693    REG: crate::Writable + crate::RegisterSpec,
694{
695    ///Next transmit value is from Tx buffer
696    #[inline(always)]
697    pub fn tx_buffer(self) -> &'a mut crate::W<REG> {
698        self.variant(CRCNEXT::TxBuffer)
699    }
700    ///Next transmit value is from Tx CRC register
701    #[inline(always)]
702    pub fn crc(self) -> &'a mut crate::W<REG> {
703        self.variant(CRCNEXT::Crc)
704    }
705}
706/**Hardware CRC calculation enable
707
708Value on reset: 0*/
709#[cfg_attr(feature = "defmt", derive(defmt::Format))]
710#[derive(Clone, Copy, Debug, PartialEq, Eq)]
711pub enum CRCEN {
712    ///0: CRC calculation disabled
713    Disabled = 0,
714    ///1: CRC calculation enabled
715    Enabled = 1,
716}
717impl From<CRCEN> for bool {
718    #[inline(always)]
719    fn from(variant: CRCEN) -> Self {
720        variant as u8 != 0
721    }
722}
723///Field `CRCEN` reader - Hardware CRC calculation enable
724pub type CRCEN_R = crate::BitReader<CRCEN>;
725impl CRCEN_R {
726    ///Get enumerated values variant
727    #[inline(always)]
728    pub const fn variant(&self) -> CRCEN {
729        match self.bits {
730            false => CRCEN::Disabled,
731            true => CRCEN::Enabled,
732        }
733    }
734    ///CRC calculation disabled
735    #[inline(always)]
736    pub fn is_disabled(&self) -> bool {
737        *self == CRCEN::Disabled
738    }
739    ///CRC calculation enabled
740    #[inline(always)]
741    pub fn is_enabled(&self) -> bool {
742        *self == CRCEN::Enabled
743    }
744}
745///Field `CRCEN` writer - Hardware CRC calculation enable
746pub type CRCEN_W<'a, REG> = crate::BitWriter<'a, REG, CRCEN>;
747impl<'a, REG> CRCEN_W<'a, REG>
748where
749    REG: crate::Writable + crate::RegisterSpec,
750{
751    ///CRC calculation disabled
752    #[inline(always)]
753    pub fn disabled(self) -> &'a mut crate::W<REG> {
754        self.variant(CRCEN::Disabled)
755    }
756    ///CRC calculation enabled
757    #[inline(always)]
758    pub fn enabled(self) -> &'a mut crate::W<REG> {
759        self.variant(CRCEN::Enabled)
760    }
761}
762/**Output enable in bidirectional mode
763
764Value on reset: 0*/
765#[cfg_attr(feature = "defmt", derive(defmt::Format))]
766#[derive(Clone, Copy, Debug, PartialEq, Eq)]
767pub enum BIDIOE {
768    ///0: Output disabled (receive-only mode)
769    OutputDisabled = 0,
770    ///1: Output enabled (transmit-only mode)
771    OutputEnabled = 1,
772}
773impl From<BIDIOE> for bool {
774    #[inline(always)]
775    fn from(variant: BIDIOE) -> Self {
776        variant as u8 != 0
777    }
778}
779///Field `BIDIOE` reader - Output enable in bidirectional mode
780pub type BIDIOE_R = crate::BitReader<BIDIOE>;
781impl BIDIOE_R {
782    ///Get enumerated values variant
783    #[inline(always)]
784    pub const fn variant(&self) -> BIDIOE {
785        match self.bits {
786            false => BIDIOE::OutputDisabled,
787            true => BIDIOE::OutputEnabled,
788        }
789    }
790    ///Output disabled (receive-only mode)
791    #[inline(always)]
792    pub fn is_output_disabled(&self) -> bool {
793        *self == BIDIOE::OutputDisabled
794    }
795    ///Output enabled (transmit-only mode)
796    #[inline(always)]
797    pub fn is_output_enabled(&self) -> bool {
798        *self == BIDIOE::OutputEnabled
799    }
800}
801///Field `BIDIOE` writer - Output enable in bidirectional mode
802pub type BIDIOE_W<'a, REG> = crate::BitWriter<'a, REG, BIDIOE>;
803impl<'a, REG> BIDIOE_W<'a, REG>
804where
805    REG: crate::Writable + crate::RegisterSpec,
806{
807    ///Output disabled (receive-only mode)
808    #[inline(always)]
809    pub fn output_disabled(self) -> &'a mut crate::W<REG> {
810        self.variant(BIDIOE::OutputDisabled)
811    }
812    ///Output enabled (transmit-only mode)
813    #[inline(always)]
814    pub fn output_enabled(self) -> &'a mut crate::W<REG> {
815        self.variant(BIDIOE::OutputEnabled)
816    }
817}
818/**Bidirectional data mode enable
819
820Value on reset: 0*/
821#[cfg_attr(feature = "defmt", derive(defmt::Format))]
822#[derive(Clone, Copy, Debug, PartialEq, Eq)]
823pub enum BIDIMODE {
824    ///0: 2-line unidirectional data mode selected
825    Unidirectional = 0,
826    ///1: 1-line bidirectional data mode selected
827    Bidirectional = 1,
828}
829impl From<BIDIMODE> for bool {
830    #[inline(always)]
831    fn from(variant: BIDIMODE) -> Self {
832        variant as u8 != 0
833    }
834}
835///Field `BIDIMODE` reader - Bidirectional data mode enable
836pub type BIDIMODE_R = crate::BitReader<BIDIMODE>;
837impl BIDIMODE_R {
838    ///Get enumerated values variant
839    #[inline(always)]
840    pub const fn variant(&self) -> BIDIMODE {
841        match self.bits {
842            false => BIDIMODE::Unidirectional,
843            true => BIDIMODE::Bidirectional,
844        }
845    }
846    ///2-line unidirectional data mode selected
847    #[inline(always)]
848    pub fn is_unidirectional(&self) -> bool {
849        *self == BIDIMODE::Unidirectional
850    }
851    ///1-line bidirectional data mode selected
852    #[inline(always)]
853    pub fn is_bidirectional(&self) -> bool {
854        *self == BIDIMODE::Bidirectional
855    }
856}
857///Field `BIDIMODE` writer - Bidirectional data mode enable
858pub type BIDIMODE_W<'a, REG> = crate::BitWriter<'a, REG, BIDIMODE>;
859impl<'a, REG> BIDIMODE_W<'a, REG>
860where
861    REG: crate::Writable + crate::RegisterSpec,
862{
863    ///2-line unidirectional data mode selected
864    #[inline(always)]
865    pub fn unidirectional(self) -> &'a mut crate::W<REG> {
866        self.variant(BIDIMODE::Unidirectional)
867    }
868    ///1-line bidirectional data mode selected
869    #[inline(always)]
870    pub fn bidirectional(self) -> &'a mut crate::W<REG> {
871        self.variant(BIDIMODE::Bidirectional)
872    }
873}
874impl R {
875    ///Bit 0 - Clock phase
876    #[inline(always)]
877    pub fn cpha(&self) -> CPHA_R {
878        CPHA_R::new((self.bits & 1) != 0)
879    }
880    ///Bit 1 - Clock polarity
881    #[inline(always)]
882    pub fn cpol(&self) -> CPOL_R {
883        CPOL_R::new(((self.bits >> 1) & 1) != 0)
884    }
885    ///Bit 2 - Master selection
886    #[inline(always)]
887    pub fn mstr(&self) -> MSTR_R {
888        MSTR_R::new(((self.bits >> 2) & 1) != 0)
889    }
890    ///Bits 3:5 - Baud rate control
891    #[inline(always)]
892    pub fn br(&self) -> BR_R {
893        BR_R::new(((self.bits >> 3) & 7) as u8)
894    }
895    ///Bit 6 - SPI enable
896    #[inline(always)]
897    pub fn spe(&self) -> SPE_R {
898        SPE_R::new(((self.bits >> 6) & 1) != 0)
899    }
900    ///Bit 7 - Frame format
901    #[inline(always)]
902    pub fn lsbfirst(&self) -> LSBFIRST_R {
903        LSBFIRST_R::new(((self.bits >> 7) & 1) != 0)
904    }
905    ///Bit 8 - Internal slave select
906    #[inline(always)]
907    pub fn ssi(&self) -> SSI_R {
908        SSI_R::new(((self.bits >> 8) & 1) != 0)
909    }
910    ///Bit 9 - Software slave management
911    #[inline(always)]
912    pub fn ssm(&self) -> SSM_R {
913        SSM_R::new(((self.bits >> 9) & 1) != 0)
914    }
915    ///Bit 10 - Receive only
916    #[inline(always)]
917    pub fn rxonly(&self) -> RXONLY_R {
918        RXONLY_R::new(((self.bits >> 10) & 1) != 0)
919    }
920    ///Bit 11 - CRC length
921    #[inline(always)]
922    pub fn crcl(&self) -> CRCL_R {
923        CRCL_R::new(((self.bits >> 11) & 1) != 0)
924    }
925    ///Bit 12 - CRC transfer next
926    #[inline(always)]
927    pub fn crcnext(&self) -> CRCNEXT_R {
928        CRCNEXT_R::new(((self.bits >> 12) & 1) != 0)
929    }
930    ///Bit 13 - Hardware CRC calculation enable
931    #[inline(always)]
932    pub fn crcen(&self) -> CRCEN_R {
933        CRCEN_R::new(((self.bits >> 13) & 1) != 0)
934    }
935    ///Bit 14 - Output enable in bidirectional mode
936    #[inline(always)]
937    pub fn bidioe(&self) -> BIDIOE_R {
938        BIDIOE_R::new(((self.bits >> 14) & 1) != 0)
939    }
940    ///Bit 15 - Bidirectional data mode enable
941    #[inline(always)]
942    pub fn bidimode(&self) -> BIDIMODE_R {
943        BIDIMODE_R::new(((self.bits >> 15) & 1) != 0)
944    }
945}
946impl core::fmt::Debug for R {
947    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
948        f.debug_struct("CR1")
949            .field("bidimode", &self.bidimode())
950            .field("bidioe", &self.bidioe())
951            .field("crcen", &self.crcen())
952            .field("crcnext", &self.crcnext())
953            .field("crcl", &self.crcl())
954            .field("rxonly", &self.rxonly())
955            .field("ssm", &self.ssm())
956            .field("ssi", &self.ssi())
957            .field("lsbfirst", &self.lsbfirst())
958            .field("spe", &self.spe())
959            .field("br", &self.br())
960            .field("mstr", &self.mstr())
961            .field("cpol", &self.cpol())
962            .field("cpha", &self.cpha())
963            .finish()
964    }
965}
966impl W {
967    ///Bit 0 - Clock phase
968    #[inline(always)]
969    pub fn cpha(&mut self) -> CPHA_W<CR1rs> {
970        CPHA_W::new(self, 0)
971    }
972    ///Bit 1 - Clock polarity
973    #[inline(always)]
974    pub fn cpol(&mut self) -> CPOL_W<CR1rs> {
975        CPOL_W::new(self, 1)
976    }
977    ///Bit 2 - Master selection
978    #[inline(always)]
979    pub fn mstr(&mut self) -> MSTR_W<CR1rs> {
980        MSTR_W::new(self, 2)
981    }
982    ///Bits 3:5 - Baud rate control
983    #[inline(always)]
984    pub fn br(&mut self) -> BR_W<CR1rs> {
985        BR_W::new(self, 3)
986    }
987    ///Bit 6 - SPI enable
988    #[inline(always)]
989    pub fn spe(&mut self) -> SPE_W<CR1rs> {
990        SPE_W::new(self, 6)
991    }
992    ///Bit 7 - Frame format
993    #[inline(always)]
994    pub fn lsbfirst(&mut self) -> LSBFIRST_W<CR1rs> {
995        LSBFIRST_W::new(self, 7)
996    }
997    ///Bit 8 - Internal slave select
998    #[inline(always)]
999    pub fn ssi(&mut self) -> SSI_W<CR1rs> {
1000        SSI_W::new(self, 8)
1001    }
1002    ///Bit 9 - Software slave management
1003    #[inline(always)]
1004    pub fn ssm(&mut self) -> SSM_W<CR1rs> {
1005        SSM_W::new(self, 9)
1006    }
1007    ///Bit 10 - Receive only
1008    #[inline(always)]
1009    pub fn rxonly(&mut self) -> RXONLY_W<CR1rs> {
1010        RXONLY_W::new(self, 10)
1011    }
1012    ///Bit 11 - CRC length
1013    #[inline(always)]
1014    pub fn crcl(&mut self) -> CRCL_W<CR1rs> {
1015        CRCL_W::new(self, 11)
1016    }
1017    ///Bit 12 - CRC transfer next
1018    #[inline(always)]
1019    pub fn crcnext(&mut self) -> CRCNEXT_W<CR1rs> {
1020        CRCNEXT_W::new(self, 12)
1021    }
1022    ///Bit 13 - Hardware CRC calculation enable
1023    #[inline(always)]
1024    pub fn crcen(&mut self) -> CRCEN_W<CR1rs> {
1025        CRCEN_W::new(self, 13)
1026    }
1027    ///Bit 14 - Output enable in bidirectional mode
1028    #[inline(always)]
1029    pub fn bidioe(&mut self) -> BIDIOE_W<CR1rs> {
1030        BIDIOE_W::new(self, 14)
1031    }
1032    ///Bit 15 - Bidirectional data mode enable
1033    #[inline(always)]
1034    pub fn bidimode(&mut self) -> BIDIMODE_W<CR1rs> {
1035        BIDIMODE_W::new(self, 15)
1036    }
1037}
1038/**control register 1
1039
1040You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1041
1042See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:CR1)*/
1043pub struct CR1rs;
1044impl crate::RegisterSpec for CR1rs {
1045    type Ux = u16;
1046}
1047///`read()` method returns [`cr1::R`](R) reader structure
1048impl crate::Readable for CR1rs {}
1049///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
1050impl crate::Writable for CR1rs {
1051    type Safety = crate::Unsafe;
1052}
1053///`reset()` method sets CR1 to value 0
1054impl crate::Resettable for CR1rs {}
stm32g0/stm32g081/spi1/cr1.rs

stm32g0/stm32g081/spi1/
cr1.rs
