stm32g0/stm32g081/
spi1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    _reserved1: [u8; 0x02],
7    cr2: CR2,
8    _reserved2: [u8; 0x02],
9    sr: SR,
10    _reserved3: [u8; 0x02],
11    _reserved_3_dr: [u8; 0x02],
12    _reserved4: [u8; 0x02],
13    crcpr: CRCPR,
14    _reserved5: [u8; 0x02],
15    rxcrcr: RXCRCR,
16    _reserved6: [u8; 0x02],
17    txcrcr: TXCRCR,
18    _reserved7: [u8; 0x02],
19    i2scfgr: I2SCFGR,
20    _reserved8: [u8; 0x02],
21    i2spr: I2SPR,
22    _reserved9: [u8; 0x03ce],
23    hwcfgr: HWCFGR,
24    verr: VERR,
25    ipidr: IPIDR,
26    sidr: SIDR,
27}
28impl RegisterBlock {
29    ///0x00 - control register 1
30    #[inline(always)]
31    pub const fn cr1(&self) -> &CR1 {
32        &self.cr1
33    }
34    ///0x04 - control register 2
35    #[inline(always)]
36    pub const fn cr2(&self) -> &CR2 {
37        &self.cr2
38    }
39    ///0x08 - status register
40    #[inline(always)]
41    pub const fn sr(&self) -> &SR {
42        &self.sr
43    }
44    ///0x0c - Direct 8-bit access to data register
45    #[inline(always)]
46    pub const fn dr8(&self) -> &DR8 {
47        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
48    }
49    ///0x0c - data register
50    #[inline(always)]
51    pub const fn dr(&self) -> &DR {
52        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
53    }
54    ///0x10 - CRC polynomial register
55    #[inline(always)]
56    pub const fn crcpr(&self) -> &CRCPR {
57        &self.crcpr
58    }
59    ///0x14 - RX CRC register
60    #[inline(always)]
61    pub const fn rxcrcr(&self) -> &RXCRCR {
62        &self.rxcrcr
63    }
64    ///0x18 - TX CRC register
65    #[inline(always)]
66    pub const fn txcrcr(&self) -> &TXCRCR {
67        &self.txcrcr
68    }
69    ///0x1c - configuration register
70    #[inline(always)]
71    pub const fn i2scfgr(&self) -> &I2SCFGR {
72        &self.i2scfgr
73    }
74    ///0x20 - prescaler register
75    #[inline(always)]
76    pub const fn i2spr(&self) -> &I2SPR {
77        &self.i2spr
78    }
79    ///0x3f0 - hardware configuration register
80    #[inline(always)]
81    pub const fn hwcfgr(&self) -> &HWCFGR {
82        &self.hwcfgr
83    }
84    ///0x3f4 - EXTI IP Version register
85    #[inline(always)]
86    pub const fn verr(&self) -> &VERR {
87        &self.verr
88    }
89    ///0x3f8 - EXTI Identification register
90    #[inline(always)]
91    pub const fn ipidr(&self) -> &IPIDR {
92        &self.ipidr
93    }
94    ///0x3fc - EXTI Size ID register
95    #[inline(always)]
96    pub const fn sidr(&self) -> &SIDR {
97        &self.sidr
98    }
99}
100/**CR1 (rw) register accessor: control register 1
101
102You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
103
104See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:CR1)
105
106For information about available fields see [`mod@cr1`] module*/
107pub type CR1 = crate::Reg<cr1::CR1rs>;
108///control register 1
109pub mod cr1;
110/**CR2 (rw) register accessor: control register 2
111
112You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
113
114See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:CR2)
115
116For information about available fields see [`mod@cr2`] module*/
117pub type CR2 = crate::Reg<cr2::CR2rs>;
118///control register 2
119pub mod cr2;
120/**SR (rw) register accessor: status register
121
122You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:SR)
125
126For information about available fields see [`mod@sr`] module*/
127pub type SR = crate::Reg<sr::SRrs>;
128///status register
129pub mod sr;
130/**DR (rw) register accessor: data register
131
132You can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:DR)
135
136For information about available fields see [`mod@dr`] module*/
137pub type DR = crate::Reg<dr::DRrs>;
138///data register
139pub mod dr;
140/**DR8 (rw) register accessor: Direct 8-bit access to data register
141
142You can [`read`](crate::Reg::read) this register and get [`dr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:DR8)
145
146For information about available fields see [`mod@dr8`] module*/
147pub type DR8 = crate::Reg<dr8::DR8rs>;
148///Direct 8-bit access to data register
149pub mod dr8;
150/**CRCPR (rw) register accessor: CRC polynomial register
151
152You can [`read`](crate::Reg::read) this register and get [`crcpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:CRCPR)
155
156For information about available fields see [`mod@crcpr`] module*/
157pub type CRCPR = crate::Reg<crcpr::CRCPRrs>;
158///CRC polynomial register
159pub mod crcpr;
160/**RXCRCR (r) register accessor: RX CRC register
161
162You can [`read`](crate::Reg::read) this register and get [`rxcrcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
163
164See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:RXCRCR)
165
166For information about available fields see [`mod@rxcrcr`] module*/
167pub type RXCRCR = crate::Reg<rxcrcr::RXCRCRrs>;
168///RX CRC register
169pub mod rxcrcr;
170/**TXCRCR (r) register accessor: TX CRC register
171
172You can [`read`](crate::Reg::read) this register and get [`txcrcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
173
174See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:TXCRCR)
175
176For information about available fields see [`mod@txcrcr`] module*/
177pub type TXCRCR = crate::Reg<txcrcr::TXCRCRrs>;
178///TX CRC register
179pub mod txcrcr;
180/**I2SCFGR (rw) register accessor: configuration register
181
182You can [`read`](crate::Reg::read) this register and get [`i2scfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2scfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:I2SCFGR)
185
186For information about available fields see [`mod@i2scfgr`] module*/
187pub type I2SCFGR = crate::Reg<i2scfgr::I2SCFGRrs>;
188///configuration register
189pub mod i2scfgr;
190/**I2SPR (rw) register accessor: prescaler register
191
192You can [`read`](crate::Reg::read) this register and get [`i2spr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2spr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
193
194See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:I2SPR)
195
196For information about available fields see [`mod@i2spr`] module*/
197pub type I2SPR = crate::Reg<i2spr::I2SPRrs>;
198///prescaler register
199pub mod i2spr;
200/**HWCFGR (r) register accessor: hardware configuration register
201
202You can [`read`](crate::Reg::read) this register and get [`hwcfgr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
203
204See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:HWCFGR)
205
206For information about available fields see [`mod@hwcfgr`] module*/
207pub type HWCFGR = crate::Reg<hwcfgr::HWCFGRrs>;
208///hardware configuration register
209pub mod hwcfgr;
210/**VERR (r) register accessor: EXTI IP Version register
211
212You can [`read`](crate::Reg::read) this register and get [`verr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
213
214See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:VERR)
215
216For information about available fields see [`mod@verr`] module*/
217pub type VERR = crate::Reg<verr::VERRrs>;
218///EXTI IP Version register
219pub mod verr;
220/**IPIDR (r) register accessor: EXTI Identification register
221
222You can [`read`](crate::Reg::read) this register and get [`ipidr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
223
224See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:IPIDR)
225
226For information about available fields see [`mod@ipidr`] module*/
227pub type IPIDR = crate::Reg<ipidr::IPIDRrs>;
228///EXTI Identification register
229pub mod ipidr;
230/**SIDR (r) register accessor: EXTI Size ID register
231
232You can [`read`](crate::Reg::read) this register and get [`sidr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
233
234See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#SPI1:SIDR)
235
236For information about available fields see [`mod@sidr`] module*/
237pub type SIDR = crate::Reg<sidr::SIDRrs>;
238///EXTI Size ID register
239pub mod sidr;
stm32g0/stm32g081/spi1.rs

stm32g0/stm32g081/
spi1.rs
