stm32g0/stm32g081/adc/ccr.rs
1///Register `CCR` reader
2pub type R = crate::R<CCRrs>;
3///Register `CCR` writer
4pub type W = crate::W<CCRrs>;
5/**ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum PRESC {
12 ///0: Input ADC clock not divided
13 Div1 = 0,
14 ///1: Input ADC clock divided by 2
15 Div2 = 1,
16 ///2: Input ADC clock divided by 4
17 Div4 = 2,
18 ///3: Input ADC clock divided by 6
19 Div6 = 3,
20 ///4: Input ADC clock divided by 8
21 Div8 = 4,
22 ///5: Input ADC clock divided by 10
23 Div10 = 5,
24 ///6: Input ADC clock divided by 12
25 Div12 = 6,
26 ///7: Input ADC clock divided by 16
27 Div16 = 7,
28 ///8: Input ADC clock divided by 32
29 Div32 = 8,
30 ///9: Input ADC clock divided by 64
31 Div64 = 9,
32 ///10: Input ADC clock divided by 128
33 Div128 = 10,
34 ///11: Input ADC clock divided by 256
35 Div256 = 11,
36}
37impl From<PRESC> for u8 {
38 #[inline(always)]
39 fn from(variant: PRESC) -> Self {
40 variant as _
41 }
42}
43impl crate::FieldSpec for PRESC {
44 type Ux = u8;
45}
46impl crate::IsEnum for PRESC {}
47///Field `PRESC` reader - ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
48pub type PRESC_R = crate::FieldReader<PRESC>;
49impl PRESC_R {
50 ///Get enumerated values variant
51 #[inline(always)]
52 pub const fn variant(&self) -> Option<PRESC> {
53 match self.bits {
54 0 => Some(PRESC::Div1),
55 1 => Some(PRESC::Div2),
56 2 => Some(PRESC::Div4),
57 3 => Some(PRESC::Div6),
58 4 => Some(PRESC::Div8),
59 5 => Some(PRESC::Div10),
60 6 => Some(PRESC::Div12),
61 7 => Some(PRESC::Div16),
62 8 => Some(PRESC::Div32),
63 9 => Some(PRESC::Div64),
64 10 => Some(PRESC::Div128),
65 11 => Some(PRESC::Div256),
66 _ => None,
67 }
68 }
69 ///Input ADC clock not divided
70 #[inline(always)]
71 pub fn is_div1(&self) -> bool {
72 *self == PRESC::Div1
73 }
74 ///Input ADC clock divided by 2
75 #[inline(always)]
76 pub fn is_div2(&self) -> bool {
77 *self == PRESC::Div2
78 }
79 ///Input ADC clock divided by 4
80 #[inline(always)]
81 pub fn is_div4(&self) -> bool {
82 *self == PRESC::Div4
83 }
84 ///Input ADC clock divided by 6
85 #[inline(always)]
86 pub fn is_div6(&self) -> bool {
87 *self == PRESC::Div6
88 }
89 ///Input ADC clock divided by 8
90 #[inline(always)]
91 pub fn is_div8(&self) -> bool {
92 *self == PRESC::Div8
93 }
94 ///Input ADC clock divided by 10
95 #[inline(always)]
96 pub fn is_div10(&self) -> bool {
97 *self == PRESC::Div10
98 }
99 ///Input ADC clock divided by 12
100 #[inline(always)]
101 pub fn is_div12(&self) -> bool {
102 *self == PRESC::Div12
103 }
104 ///Input ADC clock divided by 16
105 #[inline(always)]
106 pub fn is_div16(&self) -> bool {
107 *self == PRESC::Div16
108 }
109 ///Input ADC clock divided by 32
110 #[inline(always)]
111 pub fn is_div32(&self) -> bool {
112 *self == PRESC::Div32
113 }
114 ///Input ADC clock divided by 64
115 #[inline(always)]
116 pub fn is_div64(&self) -> bool {
117 *self == PRESC::Div64
118 }
119 ///Input ADC clock divided by 128
120 #[inline(always)]
121 pub fn is_div128(&self) -> bool {
122 *self == PRESC::Div128
123 }
124 ///Input ADC clock divided by 256
125 #[inline(always)]
126 pub fn is_div256(&self) -> bool {
127 *self == PRESC::Div256
128 }
129}
130///Field `PRESC` writer - ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
131pub type PRESC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PRESC>;
132impl<'a, REG> PRESC_W<'a, REG>
133where
134 REG: crate::Writable + crate::RegisterSpec,
135 REG::Ux: From<u8>,
136{
137 ///Input ADC clock not divided
138 #[inline(always)]
139 pub fn div1(self) -> &'a mut crate::W<REG> {
140 self.variant(PRESC::Div1)
141 }
142 ///Input ADC clock divided by 2
143 #[inline(always)]
144 pub fn div2(self) -> &'a mut crate::W<REG> {
145 self.variant(PRESC::Div2)
146 }
147 ///Input ADC clock divided by 4
148 #[inline(always)]
149 pub fn div4(self) -> &'a mut crate::W<REG> {
150 self.variant(PRESC::Div4)
151 }
152 ///Input ADC clock divided by 6
153 #[inline(always)]
154 pub fn div6(self) -> &'a mut crate::W<REG> {
155 self.variant(PRESC::Div6)
156 }
157 ///Input ADC clock divided by 8
158 #[inline(always)]
159 pub fn div8(self) -> &'a mut crate::W<REG> {
160 self.variant(PRESC::Div8)
161 }
162 ///Input ADC clock divided by 10
163 #[inline(always)]
164 pub fn div10(self) -> &'a mut crate::W<REG> {
165 self.variant(PRESC::Div10)
166 }
167 ///Input ADC clock divided by 12
168 #[inline(always)]
169 pub fn div12(self) -> &'a mut crate::W<REG> {
170 self.variant(PRESC::Div12)
171 }
172 ///Input ADC clock divided by 16
173 #[inline(always)]
174 pub fn div16(self) -> &'a mut crate::W<REG> {
175 self.variant(PRESC::Div16)
176 }
177 ///Input ADC clock divided by 32
178 #[inline(always)]
179 pub fn div32(self) -> &'a mut crate::W<REG> {
180 self.variant(PRESC::Div32)
181 }
182 ///Input ADC clock divided by 64
183 #[inline(always)]
184 pub fn div64(self) -> &'a mut crate::W<REG> {
185 self.variant(PRESC::Div64)
186 }
187 ///Input ADC clock divided by 128
188 #[inline(always)]
189 pub fn div128(self) -> &'a mut crate::W<REG> {
190 self.variant(PRESC::Div128)
191 }
192 ///Input ADC clock divided by 256
193 #[inline(always)]
194 pub fn div256(self) -> &'a mut crate::W<REG> {
195 self.variant(PRESC::Div256)
196 }
197}
198/**VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
199
200Value on reset: 0*/
201#[cfg_attr(feature = "defmt", derive(defmt::Format))]
202#[derive(Clone, Copy, Debug, PartialEq, Eq)]
203pub enum VREFEN {
204 ///0: The selected ADC channel disabled
205 Disabled = 0,
206 ///1: The selected ADC channel enabled
207 Enabled = 1,
208}
209impl From<VREFEN> for bool {
210 #[inline(always)]
211 fn from(variant: VREFEN) -> Self {
212 variant as u8 != 0
213 }
214}
215///Field `VREFEN` reader - VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
216pub type VREFEN_R = crate::BitReader<VREFEN>;
217impl VREFEN_R {
218 ///Get enumerated values variant
219 #[inline(always)]
220 pub const fn variant(&self) -> VREFEN {
221 match self.bits {
222 false => VREFEN::Disabled,
223 true => VREFEN::Enabled,
224 }
225 }
226 ///The selected ADC channel disabled
227 #[inline(always)]
228 pub fn is_disabled(&self) -> bool {
229 *self == VREFEN::Disabled
230 }
231 ///The selected ADC channel enabled
232 #[inline(always)]
233 pub fn is_enabled(&self) -> bool {
234 *self == VREFEN::Enabled
235 }
236}
237///Field `VREFEN` writer - VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
238pub type VREFEN_W<'a, REG> = crate::BitWriter<'a, REG, VREFEN>;
239impl<'a, REG> VREFEN_W<'a, REG>
240where
241 REG: crate::Writable + crate::RegisterSpec,
242{
243 ///The selected ADC channel disabled
244 #[inline(always)]
245 pub fn disabled(self) -> &'a mut crate::W<REG> {
246 self.variant(VREFEN::Disabled)
247 }
248 ///The selected ADC channel enabled
249 #[inline(always)]
250 pub fn enabled(self) -> &'a mut crate::W<REG> {
251 self.variant(VREFEN::Enabled)
252 }
253}
254///Field `TSEN` reader - Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
255pub use VREFEN_R as TSEN_R;
256///Field `VBATEN` reader - VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)
257pub use VREFEN_R as VBATEN_R;
258///Field `TSEN` writer - Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
259pub use VREFEN_W as TSEN_W;
260///Field `VBATEN` writer - VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)
261pub use VREFEN_W as VBATEN_W;
262impl R {
263 ///Bits 18:21 - ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
264 #[inline(always)]
265 pub fn presc(&self) -> PRESC_R {
266 PRESC_R::new(((self.bits >> 18) & 0x0f) as u8)
267 }
268 ///Bit 22 - VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
269 #[inline(always)]
270 pub fn vrefen(&self) -> VREFEN_R {
271 VREFEN_R::new(((self.bits >> 22) & 1) != 0)
272 }
273 ///Bit 23 - Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
274 #[inline(always)]
275 pub fn tsen(&self) -> TSEN_R {
276 TSEN_R::new(((self.bits >> 23) & 1) != 0)
277 }
278 ///Bit 24 - VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)
279 #[inline(always)]
280 pub fn vbaten(&self) -> VBATEN_R {
281 VBATEN_R::new(((self.bits >> 24) & 1) != 0)
282 }
283}
284impl core::fmt::Debug for R {
285 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
286 f.debug_struct("CCR")
287 .field("presc", &self.presc())
288 .field("vrefen", &self.vrefen())
289 .field("tsen", &self.tsen())
290 .field("vbaten", &self.vbaten())
291 .finish()
292 }
293}
294impl W {
295 ///Bits 18:21 - ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
296 #[inline(always)]
297 pub fn presc(&mut self) -> PRESC_W<CCRrs> {
298 PRESC_W::new(self, 18)
299 }
300 ///Bit 22 - VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
301 #[inline(always)]
302 pub fn vrefen(&mut self) -> VREFEN_W<CCRrs> {
303 VREFEN_W::new(self, 22)
304 }
305 ///Bit 23 - Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
306 #[inline(always)]
307 pub fn tsen(&mut self) -> TSEN_W<CCRrs> {
308 TSEN_W::new(self, 23)
309 }
310 ///Bit 24 - VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)
311 #[inline(always)]
312 pub fn vbaten(&mut self) -> VBATEN_W<CCRrs> {
313 VBATEN_W::new(self, 24)
314 }
315}
316/**ADC common configuration register
317
318You can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
319
320See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#ADC:CCR)*/
321pub struct CCRrs;
322impl crate::RegisterSpec for CCRrs {
323 type Ux = u32;
324}
325///`read()` method returns [`ccr::R`](R) reader structure
326impl crate::Readable for CCRrs {}
327///`write(|w| ..)` method takes [`ccr::W`](W) writer structure
328impl crate::Writable for CCRrs {
329 type Safety = crate::Unsafe;
330}
331///`reset()` method sets CCR to value 0
332impl crate::Resettable for CCRrs {}