stm32g0/stm32g070/tim15/
dcr.rs

1///Register `DCR` reader
2pub type R = crate::R<DCRrs>;
3///Register `DCR` writer
4pub type W = crate::W<DCRrs>;
5///Field `DBA` reader - DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
6pub type DBA_R = crate::FieldReader;
7///Field `DBA` writer - DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
8pub type DBA_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9///Field `DBL` reader - DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
10pub type DBL_R = crate::FieldReader;
11///Field `DBL` writer - DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
12pub type DBL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13impl R {
14    ///Bits 0:4 - DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
15    #[inline(always)]
16    pub fn dba(&self) -> DBA_R {
17        DBA_R::new((self.bits & 0x1f) as u8)
18    }
19    ///Bits 8:12 - DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
20    #[inline(always)]
21    pub fn dbl(&self) -> DBL_R {
22        DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
23    }
24}
25impl core::fmt::Debug for R {
26    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27        f.debug_struct("DCR")
28            .field("dba", &self.dba())
29            .field("dbl", &self.dbl())
30            .finish()
31    }
32}
33impl W {
34    ///Bits 0:4 - DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ...
35    #[inline(always)]
36    pub fn dba(&mut self) -> DBA_W<DCRrs> {
37        DBA_W::new(self, 0)
38    }
39    ///Bits 8:12 - DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
40    #[inline(always)]
41    pub fn dbl(&mut self) -> DBL_W<DCRrs> {
42        DBL_W::new(self, 8)
43    }
44}
45/**DMA control register
46
47You can [`read`](crate::Reg::read) this register and get [`dcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
48
49See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G070.html#TIM15:DCR)*/
50pub struct DCRrs;
51impl crate::RegisterSpec for DCRrs {
52    type Ux = u32;
53}
54///`read()` method returns [`dcr::R`](R) reader structure
55impl crate::Readable for DCRrs {}
56///`write(|w| ..)` method takes [`dcr::W`](W) writer structure
57impl crate::Writable for DCRrs {
58    type Safety = crate::Unsafe;
59}
60///`reset()` method sets DCR to value 0
61impl crate::Resettable for DCRrs {}
stm32g0/stm32g070/tim15/dcr.rs

stm32g0/stm32g070/tim15/
dcr.rs
