stm32g0/stm32g070/rtc/misr.rs
1///Register `MISR` reader
2pub type R = crate::R<MISRrs>;
3/**Alarm %s masked flag
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum ALRAMF {
9 ///1: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
10 Match = 1,
11}
12impl From<ALRAMF> for bool {
13 #[inline(always)]
14 fn from(variant: ALRAMF) -> Self {
15 variant as u8 != 0
16 }
17}
18///Field `ALRMF(A,B)` reader - Alarm %s masked flag
19pub type ALRMF_R = crate::BitReader<ALRAMF>;
20impl ALRMF_R {
21 ///Get enumerated values variant
22 #[inline(always)]
23 pub const fn variant(&self) -> Option<ALRAMF> {
24 match self.bits {
25 true => Some(ALRAMF::Match),
26 _ => None,
27 }
28 }
29 ///This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
30 #[inline(always)]
31 pub fn is_match(&self) -> bool {
32 *self == ALRAMF::Match
33 }
34}
35/**Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
36
37Value on reset: 0*/
38#[cfg_attr(feature = "defmt", derive(defmt::Format))]
39#[derive(Clone, Copy, Debug, PartialEq, Eq)]
40pub enum WUTMF {
41 ///1: This flag is set by hardware when the wakeup auto-reload counter reaches 0
42 Zero = 1,
43}
44impl From<WUTMF> for bool {
45 #[inline(always)]
46 fn from(variant: WUTMF) -> Self {
47 variant as u8 != 0
48 }
49}
50///Field `WUTMF` reader - Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
51pub type WUTMF_R = crate::BitReader<WUTMF>;
52impl WUTMF_R {
53 ///Get enumerated values variant
54 #[inline(always)]
55 pub const fn variant(&self) -> Option<WUTMF> {
56 match self.bits {
57 true => Some(WUTMF::Zero),
58 _ => None,
59 }
60 }
61 ///This flag is set by hardware when the wakeup auto-reload counter reaches 0
62 #[inline(always)]
63 pub fn is_zero(&self) -> bool {
64 *self == WUTMF::Zero
65 }
66}
67/**Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
68
69Value on reset: 0*/
70#[cfg_attr(feature = "defmt", derive(defmt::Format))]
71#[derive(Clone, Copy, Debug, PartialEq, Eq)]
72pub enum TSMF {
73 ///1: This flag is set by hardware when a time-stamp event occurs
74 TimestampEvent = 1,
75}
76impl From<TSMF> for bool {
77 #[inline(always)]
78 fn from(variant: TSMF) -> Self {
79 variant as u8 != 0
80 }
81}
82///Field `TSMF` reader - Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
83pub type TSMF_R = crate::BitReader<TSMF>;
84impl TSMF_R {
85 ///Get enumerated values variant
86 #[inline(always)]
87 pub const fn variant(&self) -> Option<TSMF> {
88 match self.bits {
89 true => Some(TSMF::TimestampEvent),
90 _ => None,
91 }
92 }
93 ///This flag is set by hardware when a time-stamp event occurs
94 #[inline(always)]
95 pub fn is_timestamp_event(&self) -> bool {
96 *self == TSMF::TimestampEvent
97 }
98}
99/**Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
100
101Value on reset: 0*/
102#[cfg_attr(feature = "defmt", derive(defmt::Format))]
103#[derive(Clone, Copy, Debug, PartialEq, Eq)]
104pub enum TSOVMF {
105 ///1: This flag is set by hardware when a time-stamp event occurs while TSF is already set
106 Overflow = 1,
107}
108impl From<TSOVMF> for bool {
109 #[inline(always)]
110 fn from(variant: TSOVMF) -> Self {
111 variant as u8 != 0
112 }
113}
114///Field `TSOVMF` reader - Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
115pub type TSOVMF_R = crate::BitReader<TSOVMF>;
116impl TSOVMF_R {
117 ///Get enumerated values variant
118 #[inline(always)]
119 pub const fn variant(&self) -> Option<TSOVMF> {
120 match self.bits {
121 true => Some(TSOVMF::Overflow),
122 _ => None,
123 }
124 }
125 ///This flag is set by hardware when a time-stamp event occurs while TSF is already set
126 #[inline(always)]
127 pub fn is_overflow(&self) -> bool {
128 *self == TSOVMF::Overflow
129 }
130}
131/**Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised.
132
133Value on reset: 0*/
134#[cfg_attr(feature = "defmt", derive(defmt::Format))]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum ITSMF {
137 ///1: This flag is set by hardware when a timestamp on the internal event occurs
138 TimestampEvent = 1,
139}
140impl From<ITSMF> for bool {
141 #[inline(always)]
142 fn from(variant: ITSMF) -> Self {
143 variant as u8 != 0
144 }
145}
146///Field `ITSMF` reader - Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised.
147pub type ITSMF_R = crate::BitReader<ITSMF>;
148impl ITSMF_R {
149 ///Get enumerated values variant
150 #[inline(always)]
151 pub const fn variant(&self) -> Option<ITSMF> {
152 match self.bits {
153 true => Some(ITSMF::TimestampEvent),
154 _ => None,
155 }
156 }
157 ///This flag is set by hardware when a timestamp on the internal event occurs
158 #[inline(always)]
159 pub fn is_timestamp_event(&self) -> bool {
160 *self == ITSMF::TimestampEvent
161 }
162}
163impl R {
164 ///Alarm (A,B) masked flag
165 ///
166 ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAMF` field.</div>
167 #[inline(always)]
168 pub fn alrmf(&self, n: u8) -> ALRMF_R {
169 #[allow(clippy::no_effect)]
170 [(); 2][n as usize];
171 ALRMF_R::new(((self.bits >> n) & 1) != 0)
172 }
173 ///Iterator for array of:
174 ///Alarm (A,B) masked flag
175 #[inline(always)]
176 pub fn alrmf_iter(&self) -> impl Iterator<Item = ALRMF_R> + '_ {
177 (0..2).map(move |n| ALRMF_R::new(((self.bits >> n) & 1) != 0))
178 }
179 ///Bit 0 - Alarm A masked flag
180 #[inline(always)]
181 pub fn alramf(&self) -> ALRMF_R {
182 ALRMF_R::new((self.bits & 1) != 0)
183 }
184 ///Bit 1 - Alarm B masked flag
185 #[inline(always)]
186 pub fn alrbmf(&self) -> ALRMF_R {
187 ALRMF_R::new(((self.bits >> 1) & 1) != 0)
188 }
189 ///Bit 2 - Wakeup timer masked flag This flag is set by hardware when the wakeup timer interrupt occurs. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.
190 #[inline(always)]
191 pub fn wutmf(&self) -> WUTMF_R {
192 WUTMF_R::new(((self.bits >> 2) & 1) != 0)
193 }
194 ///Bit 3 - Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs. If ITSF flag is set, TSF must be cleared together with ITSF.
195 #[inline(always)]
196 pub fn tsmf(&self) -> TSMF_R {
197 TSMF_R::new(((self.bits >> 3) & 1) != 0)
198 }
199 ///Bit 4 - Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
200 #[inline(always)]
201 pub fn tsovmf(&self) -> TSOVMF_R {
202 TSOVMF_R::new(((self.bits >> 4) & 1) != 0)
203 }
204 ///Bit 5 - Internal timestamp masked flag This flag is set by hardware when a timestamp on the internal event occurs and timestampinterrupt is raised.
205 #[inline(always)]
206 pub fn itsmf(&self) -> ITSMF_R {
207 ITSMF_R::new(((self.bits >> 5) & 1) != 0)
208 }
209}
210impl core::fmt::Debug for R {
211 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
212 f.debug_struct("MISR")
213 .field("alramf", &self.alramf())
214 .field("alrbmf", &self.alrbmf())
215 .field("wutmf", &self.wutmf())
216 .field("tsmf", &self.tsmf())
217 .field("tsovmf", &self.tsovmf())
218 .field("itsmf", &self.itsmf())
219 .finish()
220 }
221}
222/**RTC masked interrupt status register
223
224You can [`read`](crate::Reg::read) this register and get [`misr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
225
226See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G070.html#RTC:MISR)*/
227pub struct MISRrs;
228impl crate::RegisterSpec for MISRrs {
229 type Ux = u32;
230}
231///`read()` method returns [`misr::R`](R) reader structure
232impl crate::Readable for MISRrs {}
233///`reset()` method sets MISR to value 0
234impl crate::Resettable for MISRrs {}