stm32g0/stm32g041/rng/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `RNGEN` reader - Random number generator enable
6pub type RNGEN_R = crate::BitReader;
7///Field `RNGEN` writer - Random number generator enable
8pub type RNGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `IE` reader - Interrupt enable
10pub type IE_R = crate::BitReader;
11///Field `IE` writer - Interrupt enable
12pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CED` reader - Clock error detection
14pub type CED_R = crate::BitReader;
15///Field `CED` writer - Clock error detection
16pub type CED_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `BYP` reader - Bypass mode enable
18pub type BYP_R = crate::BitReader;
19///Field `BYP` writer - Bypass mode enable
20pub type BYP_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    ///Bit 2 - Random number generator enable
23    #[inline(always)]
24    pub fn rngen(&self) -> RNGEN_R {
25        RNGEN_R::new(((self.bits >> 2) & 1) != 0)
26    }
27    ///Bit 3 - Interrupt enable
28    #[inline(always)]
29    pub fn ie(&self) -> IE_R {
30        IE_R::new(((self.bits >> 3) & 1) != 0)
31    }
32    ///Bit 5 - Clock error detection
33    #[inline(always)]
34    pub fn ced(&self) -> CED_R {
35        CED_R::new(((self.bits >> 5) & 1) != 0)
36    }
37    ///Bit 6 - Bypass mode enable
38    #[inline(always)]
39    pub fn byp(&self) -> BYP_R {
40        BYP_R::new(((self.bits >> 6) & 1) != 0)
41    }
42}
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("CR")
46            .field("rngen", &self.rngen())
47            .field("ie", &self.ie())
48            .field("ced", &self.ced())
49            .field("byp", &self.byp())
50            .finish()
51    }
52}
53impl W {
54    ///Bit 2 - Random number generator enable
55    #[inline(always)]
56    pub fn rngen(&mut self) -> RNGEN_W<CRrs> {
57        RNGEN_W::new(self, 2)
58    }
59    ///Bit 3 - Interrupt enable
60    #[inline(always)]
61    pub fn ie(&mut self) -> IE_W<CRrs> {
62        IE_W::new(self, 3)
63    }
64    ///Bit 5 - Clock error detection
65    #[inline(always)]
66    pub fn ced(&mut self) -> CED_W<CRrs> {
67        CED_W::new(self, 5)
68    }
69    ///Bit 6 - Bypass mode enable
70    #[inline(always)]
71    pub fn byp(&mut self) -> BYP_W<CRrs> {
72        BYP_W::new(self, 6)
73    }
74}
75/**control register
76
77You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#RNG:CR)*/
80pub struct CRrs;
81impl crate::RegisterSpec for CRrs {
82    type Ux = u32;
83}
84///`read()` method returns [`cr::R`](R) reader structure
85impl crate::Readable for CRrs {}
86///`write(|w| ..)` method takes [`cr::W`](W) writer structure
87impl crate::Writable for CRrs {
88    type Safety = crate::Unsafe;
89}
90///`reset()` method sets CR to value 0
91impl crate::Resettable for CRrs {}