stm32g0/stm32g041/exti/
exticr3.rs

1///Register `EXTICR3` reader
2pub type R = crate::R<EXTICR3rs>;
3///Register `EXTICR3` writer
4pub type W = crate::W<EXTICR3rs>;
5///GPIO port selection
6pub use super::exticr1::EXTI0;
7///Field `EXTI8` reader - GPIO port selection
8pub use super::exticr1::EXTI0_R as EXTI8_R;
9///Field `EXTI9` reader - GPIO port selection
10pub use super::exticr1::EXTI0_R as EXTI9_R;
11///Field `EXTI10` reader - GPIO port selection
12pub use super::exticr1::EXTI0_R as EXTI10_R;
13///Field `EXTI11` reader - GPIO port selection
14pub use super::exticr1::EXTI0_R as EXTI11_R;
15///Field `EXTI8` writer - GPIO port selection
16pub use super::exticr1::EXTI0_W as EXTI8_W;
17///Field `EXTI9` writer - GPIO port selection
18pub use super::exticr1::EXTI0_W as EXTI9_W;
19///Field `EXTI10` writer - GPIO port selection
20pub use super::exticr1::EXTI0_W as EXTI10_W;
21///Field `EXTI11` writer - GPIO port selection
22pub use super::exticr1::EXTI0_W as EXTI11_W;
23impl R {
24    ///Bits 0:7 - GPIO port selection
25    #[inline(always)]
26    pub fn exti8(&self) -> EXTI8_R {
27        EXTI8_R::new((self.bits & 0xff) as u8)
28    }
29    ///Bits 8:15 - GPIO port selection
30    #[inline(always)]
31    pub fn exti9(&self) -> EXTI9_R {
32        EXTI9_R::new(((self.bits >> 8) & 0xff) as u8)
33    }
34    ///Bits 16:23 - GPIO port selection
35    #[inline(always)]
36    pub fn exti10(&self) -> EXTI10_R {
37        EXTI10_R::new(((self.bits >> 16) & 0xff) as u8)
38    }
39    ///Bits 24:31 - GPIO port selection
40    #[inline(always)]
41    pub fn exti11(&self) -> EXTI11_R {
42        EXTI11_R::new(((self.bits >> 24) & 0xff) as u8)
43    }
44}
45impl core::fmt::Debug for R {
46    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
47        f.debug_struct("EXTICR3")
48            .field("exti8", &self.exti8())
49            .field("exti9", &self.exti9())
50            .field("exti10", &self.exti10())
51            .field("exti11", &self.exti11())
52            .finish()
53    }
54}
55impl W {
56    ///Bits 0:7 - GPIO port selection
57    #[inline(always)]
58    pub fn exti8(&mut self) -> EXTI8_W<EXTICR3rs> {
59        EXTI8_W::new(self, 0)
60    }
61    ///Bits 8:15 - GPIO port selection
62    #[inline(always)]
63    pub fn exti9(&mut self) -> EXTI9_W<EXTICR3rs> {
64        EXTI9_W::new(self, 8)
65    }
66    ///Bits 16:23 - GPIO port selection
67    #[inline(always)]
68    pub fn exti10(&mut self) -> EXTI10_W<EXTICR3rs> {
69        EXTI10_W::new(self, 16)
70    }
71    ///Bits 24:31 - GPIO port selection
72    #[inline(always)]
73    pub fn exti11(&mut self) -> EXTI11_W<EXTICR3rs> {
74        EXTI11_W::new(self, 24)
75    }
76}
77/**EXTI external interrupt selection register
78
79You can [`read`](crate::Reg::read) this register and get [`exticr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
80
81See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#EXTI:EXTICR3)*/
82pub struct EXTICR3rs;
83impl crate::RegisterSpec for EXTICR3rs {
84    type Ux = u32;
85}
86///`read()` method returns [`exticr3::R`](R) reader structure
87impl crate::Readable for EXTICR3rs {}
88///`write(|w| ..)` method takes [`exticr3::W`](W) writer structure
89impl crate::Writable for EXTICR3rs {
90    type Safety = crate::Unsafe;
91}
92///`reset()` method sets EXTICR3 to value 0
93impl crate::Resettable for EXTICR3rs {}
stm32g0/stm32g041/exti/exticr3.rs

stm32g0/stm32g041/exti/
exticr3.rs
