Struct stm32g0::stm32g0x0::dac::dac_sr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn dmaudr1(&self) -> DMAUDR1R

Bit 13 - DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn cal_flag1(&self) -> CAL_FLAG1R

Bit 14 - DAC Channel 1 calibration offset status This bit is set and cleared by hardware

pub fn bwst1(&self) -> BWST1R

Bit 15 - DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).

pub fn dmaudr2(&self) -> DMAUDR2R

Bit 29 - DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).

pub fn cal_flag2(&self) -> CAL_FLAG2R

Bit 30 - DAC Channel 2 calibration offset status This bit is set and cleared by hardware

pub fn bwst2(&self) -> BWST2R

Bit 31 - DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).