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#[doc = r" Value read from the register"]
pub struct R {
    bits: u32,
}
impl super::HWCFGR {
    #[doc = r" Reads the contents of the register"]
    #[inline]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
}
#[doc = r" Value of the field"]
pub struct CRCCFGR {
    bits: u8,
}
impl CRCCFGR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct I2SCFGR {
    bits: u8,
}
impl I2SCFGR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct I2SCKCFGR {
    bits: u8,
}
impl I2SCKCFGR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct DSCFGR {
    bits: u8,
}
impl DSCFGR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r" Value of the field"]
pub struct NSSCFGR {
    bits: u8,
}
impl NSSCFGR {
    #[doc = r" Value of the field as raw bits"]
    #[inline]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
impl R {
    #[doc = r" Value of the register as raw bits"]
    #[inline]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 0:3 - CRC capable at SPI mode"]
    #[inline]
    pub fn crccfg(&self) -> CRCCFGR {
        let bits = {
            const MASK: u8 = 15;
            const OFFSET: u8 = 0;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        CRCCFGR { bits }
    }
    #[doc = "Bits 4:7 - I2S mode implementation"]
    #[inline]
    pub fn i2scfg(&self) -> I2SCFGR {
        let bits = {
            const MASK: u8 = 15;
            const OFFSET: u8 = 4;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        I2SCFGR { bits }
    }
    #[doc = "Bits 8:11 - I2S master clock generator at I2S mode"]
    #[inline]
    pub fn i2sckcfg(&self) -> I2SCKCFGR {
        let bits = {
            const MASK: u8 = 15;
            const OFFSET: u8 = 8;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        I2SCKCFGR { bits }
    }
    #[doc = "Bits 12:15 - SPI data size configuration"]
    #[inline]
    pub fn dscfg(&self) -> DSCFGR {
        let bits = {
            const MASK: u8 = 15;
            const OFFSET: u8 = 12;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        DSCFGR { bits }
    }
    #[doc = "Bits 16:19 - NSS pulse feature enhancement at SPI master"]
    #[inline]
    pub fn nsscfg(&self) -> NSSCFGR {
        let bits = {
            const MASK: u8 = 15;
            const OFFSET: u8 = 16;
            ((self.bits >> OFFSET) & MASK as u32) as u8
        };
        NSSCFGR { bits }
    }
}