stm32g0/stm32g0c1/tim2/
ccmr2_input.rs

1///Register `CCMR2_Input` reader
2pub type R = crate::R<CCMR2_INPUTrs>;
3///Register `CCMR2_Input` writer
4pub type W = crate::W<CCMR2_INPUTrs>;
5/**Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum CC3S {
12    ///1: CC3 channel is configured as input, IC3 is mapped on TI3
13    Ti3 = 1,
14    ///2: CC3 channel is configured as input, IC3 is mapped on TI4
15    Ti4 = 2,
16    ///3: CC3 channel is configured as input, IC3 is mapped on TRC
17    Trc = 3,
18}
19impl From<CC3S> for u8 {
20    #[inline(always)]
21    fn from(variant: CC3S) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for CC3S {
26    type Ux = u8;
27}
28impl crate::IsEnum for CC3S {}
29///Field `CC3S` reader - Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
30pub type CC3S_R = crate::FieldReader<CC3S>;
31impl CC3S_R {
32    ///Get enumerated values variant
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<CC3S> {
35        match self.bits {
36            1 => Some(CC3S::Ti3),
37            2 => Some(CC3S::Ti4),
38            3 => Some(CC3S::Trc),
39            _ => None,
40        }
41    }
42    ///CC3 channel is configured as input, IC3 is mapped on TI3
43    #[inline(always)]
44    pub fn is_ti3(&self) -> bool {
45        *self == CC3S::Ti3
46    }
47    ///CC3 channel is configured as input, IC3 is mapped on TI4
48    #[inline(always)]
49    pub fn is_ti4(&self) -> bool {
50        *self == CC3S::Ti4
51    }
52    ///CC3 channel is configured as input, IC3 is mapped on TRC
53    #[inline(always)]
54    pub fn is_trc(&self) -> bool {
55        *self == CC3S::Trc
56    }
57}
58///Field `CC3S` writer - Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
59pub type CC3S_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CC3S>;
60impl<'a, REG> CC3S_W<'a, REG>
61where
62    REG: crate::Writable + crate::RegisterSpec,
63    REG::Ux: From<u8>,
64{
65    ///CC3 channel is configured as input, IC3 is mapped on TI3
66    #[inline(always)]
67    pub fn ti3(self) -> &'a mut crate::W<REG> {
68        self.variant(CC3S::Ti3)
69    }
70    ///CC3 channel is configured as input, IC3 is mapped on TI4
71    #[inline(always)]
72    pub fn ti4(self) -> &'a mut crate::W<REG> {
73        self.variant(CC3S::Ti4)
74    }
75    ///CC3 channel is configured as input, IC3 is mapped on TRC
76    #[inline(always)]
77    pub fn trc(self) -> &'a mut crate::W<REG> {
78        self.variant(CC3S::Trc)
79    }
80}
81///Input capture %s filter
82pub use super::ccmr1_input::ICFILTER;
83///Field `ICF(3-4)` reader - Input capture %s filter
84pub use super::ccmr1_input::ICF_R;
85///Field `ICF(3-4)` writer - Input capture %s filter
86pub use super::ccmr1_input::ICF_W;
87///Input capture %s prescaler
88pub use super::ccmr1_input::ICPRESCALER;
89///Field `ICPSC(3-4)` reader - Input capture %s prescaler
90pub use super::ccmr1_input::ICPSC_R;
91///Field `ICPSC(3-4)` writer - Input capture %s prescaler
92pub use super::ccmr1_input::ICPSC_W;
93/**Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
94
95Value on reset: 0*/
96#[cfg_attr(feature = "defmt", derive(defmt::Format))]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98#[repr(u8)]
99pub enum CC4S {
100    ///1: CC4 channel is configured as input, IC4 is mapped on TI4
101    Ti4 = 1,
102    ///2: CC4 channel is configured as input, IC4 is mapped on TI3
103    Ti3 = 2,
104    ///3: CC4 channel is configured as input, IC4 is mapped on TRC
105    Trc = 3,
106}
107impl From<CC4S> for u8 {
108    #[inline(always)]
109    fn from(variant: CC4S) -> Self {
110        variant as _
111    }
112}
113impl crate::FieldSpec for CC4S {
114    type Ux = u8;
115}
116impl crate::IsEnum for CC4S {}
117///Field `CC4S` reader - Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
118pub type CC4S_R = crate::FieldReader<CC4S>;
119impl CC4S_R {
120    ///Get enumerated values variant
121    #[inline(always)]
122    pub const fn variant(&self) -> Option<CC4S> {
123        match self.bits {
124            1 => Some(CC4S::Ti4),
125            2 => Some(CC4S::Ti3),
126            3 => Some(CC4S::Trc),
127            _ => None,
128        }
129    }
130    ///CC4 channel is configured as input, IC4 is mapped on TI4
131    #[inline(always)]
132    pub fn is_ti4(&self) -> bool {
133        *self == CC4S::Ti4
134    }
135    ///CC4 channel is configured as input, IC4 is mapped on TI3
136    #[inline(always)]
137    pub fn is_ti3(&self) -> bool {
138        *self == CC4S::Ti3
139    }
140    ///CC4 channel is configured as input, IC4 is mapped on TRC
141    #[inline(always)]
142    pub fn is_trc(&self) -> bool {
143        *self == CC4S::Trc
144    }
145}
146///Field `CC4S` writer - Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
147pub type CC4S_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CC4S>;
148impl<'a, REG> CC4S_W<'a, REG>
149where
150    REG: crate::Writable + crate::RegisterSpec,
151    REG::Ux: From<u8>,
152{
153    ///CC4 channel is configured as input, IC4 is mapped on TI4
154    #[inline(always)]
155    pub fn ti4(self) -> &'a mut crate::W<REG> {
156        self.variant(CC4S::Ti4)
157    }
158    ///CC4 channel is configured as input, IC4 is mapped on TI3
159    #[inline(always)]
160    pub fn ti3(self) -> &'a mut crate::W<REG> {
161        self.variant(CC4S::Ti3)
162    }
163    ///CC4 channel is configured as input, IC4 is mapped on TRC
164    #[inline(always)]
165    pub fn trc(self) -> &'a mut crate::W<REG> {
166        self.variant(CC4S::Trc)
167    }
168}
169impl R {
170    ///Bits 0:1 - Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
171    #[inline(always)]
172    pub fn cc3s(&self) -> CC3S_R {
173        CC3S_R::new((self.bits & 3) as u8)
174    }
175    ///Input capture (3-4) prescaler
176    ///
177    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC3PSC` field.</div>
178    #[inline(always)]
179    pub fn icpsc(&self, n: u8) -> ICPSC_R {
180        #[allow(clippy::no_effect)]
181        [(); 2][n as usize];
182        ICPSC_R::new(((self.bits >> (n * 8 + 2)) & 3) as u8)
183    }
184    ///Iterator for array of:
185    ///Input capture (3-4) prescaler
186    #[inline(always)]
187    pub fn icpsc_iter(&self) -> impl Iterator<Item = ICPSC_R> + '_ {
188        (0..2).map(move |n| ICPSC_R::new(((self.bits >> (n * 8 + 2)) & 3) as u8))
189    }
190    ///Bits 2:3 - Input capture 3 prescaler
191    #[inline(always)]
192    pub fn ic3psc(&self) -> ICPSC_R {
193        ICPSC_R::new(((self.bits >> 2) & 3) as u8)
194    }
195    ///Bits 10:11 - Input capture 4 prescaler
196    #[inline(always)]
197    pub fn ic4psc(&self) -> ICPSC_R {
198        ICPSC_R::new(((self.bits >> 10) & 3) as u8)
199    }
200    ///Input capture (3-4) filter
201    ///
202    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC3F` field.</div>
203    #[inline(always)]
204    pub fn icf(&self, n: u8) -> ICF_R {
205        #[allow(clippy::no_effect)]
206        [(); 2][n as usize];
207        ICF_R::new(((self.bits >> (n * 8 + 4)) & 0x0f) as u8)
208    }
209    ///Iterator for array of:
210    ///Input capture (3-4) filter
211    #[inline(always)]
212    pub fn icf_iter(&self) -> impl Iterator<Item = ICF_R> + '_ {
213        (0..2).map(move |n| ICF_R::new(((self.bits >> (n * 8 + 4)) & 0x0f) as u8))
214    }
215    ///Bits 4:7 - Input capture 3 filter
216    #[inline(always)]
217    pub fn ic3f(&self) -> ICF_R {
218        ICF_R::new(((self.bits >> 4) & 0x0f) as u8)
219    }
220    ///Bits 12:15 - Input capture 4 filter
221    #[inline(always)]
222    pub fn ic4f(&self) -> ICF_R {
223        ICF_R::new(((self.bits >> 12) & 0x0f) as u8)
224    }
225    ///Bits 8:9 - Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
226    #[inline(always)]
227    pub fn cc4s(&self) -> CC4S_R {
228        CC4S_R::new(((self.bits >> 8) & 3) as u8)
229    }
230}
231impl core::fmt::Debug for R {
232    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
233        f.debug_struct("CCMR2_Input")
234            .field("ic3f", &self.ic3f())
235            .field("ic4f", &self.ic4f())
236            .field("ic3psc", &self.ic3psc())
237            .field("ic4psc", &self.ic4psc())
238            .field("cc4s", &self.cc4s())
239            .field("cc3s", &self.cc3s())
240            .finish()
241    }
242}
243impl W {
244    ///Bits 0:1 - Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
245    #[inline(always)]
246    pub fn cc3s(&mut self) -> CC3S_W<CCMR2_INPUTrs> {
247        CC3S_W::new(self, 0)
248    }
249    ///Input capture (3-4) prescaler
250    ///
251    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC3PSC` field.</div>
252    #[inline(always)]
253    pub fn icpsc(&mut self, n: u8) -> ICPSC_W<CCMR2_INPUTrs> {
254        #[allow(clippy::no_effect)]
255        [(); 2][n as usize];
256        ICPSC_W::new(self, n * 8 + 2)
257    }
258    ///Bits 2:3 - Input capture 3 prescaler
259    #[inline(always)]
260    pub fn ic3psc(&mut self) -> ICPSC_W<CCMR2_INPUTrs> {
261        ICPSC_W::new(self, 2)
262    }
263    ///Bits 10:11 - Input capture 4 prescaler
264    #[inline(always)]
265    pub fn ic4psc(&mut self) -> ICPSC_W<CCMR2_INPUTrs> {
266        ICPSC_W::new(self, 10)
267    }
268    ///Input capture (3-4) filter
269    ///
270    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC3F` field.</div>
271    #[inline(always)]
272    pub fn icf(&mut self, n: u8) -> ICF_W<CCMR2_INPUTrs> {
273        #[allow(clippy::no_effect)]
274        [(); 2][n as usize];
275        ICF_W::new(self, n * 8 + 4)
276    }
277    ///Bits 4:7 - Input capture 3 filter
278    #[inline(always)]
279    pub fn ic3f(&mut self) -> ICF_W<CCMR2_INPUTrs> {
280        ICF_W::new(self, 4)
281    }
282    ///Bits 12:15 - Input capture 4 filter
283    #[inline(always)]
284    pub fn ic4f(&mut self) -> ICF_W<CCMR2_INPUTrs> {
285        ICF_W::new(self, 12)
286    }
287    ///Bits 8:9 - Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
288    #[inline(always)]
289    pub fn cc4s(&mut self) -> CC4S_W<CCMR2_INPUTrs> {
290        CC4S_W::new(self, 8)
291    }
292}
293/**capture/compare mode register 2 (input mode)
294
295You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
296
297See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM2:CCMR2_Input)*/
298pub struct CCMR2_INPUTrs;
299impl crate::RegisterSpec for CCMR2_INPUTrs {
300    type Ux = u32;
301}
302///`read()` method returns [`ccmr2_input::R`](R) reader structure
303impl crate::Readable for CCMR2_INPUTrs {}
304///`write(|w| ..)` method takes [`ccmr2_input::W`](W) writer structure
305impl crate::Writable for CCMR2_INPUTrs {
306    type Safety = crate::Unsafe;
307}
308///`reset()` method sets CCMR2_Input to value 0
309impl crate::Resettable for CCMR2_INPUTrs {}
stm32g0/stm32g0c1/tim2/ccmr2_input.rs

stm32g0/stm32g0c1/tim2/
ccmr2_input.rs
