stm32g0/stm32g0b0/tim14/
dier.rs

1///Register `DIER` reader
2pub type R = crate::R<DIERrs>;
3///Register `DIER` writer
4pub type W = crate::W<DIERrs>;
5/**Update interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIE {
11    ///0: Update interrupt disabled
12    Disabled = 0,
13    ///1: Update interrupt enabled
14    Enabled = 1,
15}
16impl From<UIE> for bool {
17    #[inline(always)]
18    fn from(variant: UIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIE` reader - Update interrupt enable
23pub type UIE_R = crate::BitReader<UIE>;
24impl UIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIE {
28        match self.bits {
29            false => UIE::Disabled,
30            true => UIE::Enabled,
31        }
32    }
33    ///Update interrupt disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == UIE::Disabled
37    }
38    ///Update interrupt enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == UIE::Enabled
42    }
43}
44///Field `UIE` writer - Update interrupt enable
45pub type UIE_W<'a, REG> = crate::BitWriter<'a, REG, UIE>;
46impl<'a, REG> UIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Update interrupt disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(UIE::Disabled)
54    }
55    ///Update interrupt enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(UIE::Enabled)
59    }
60}
61/**Capture/Compare %s interrupt enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1IE {
67    ///0: CCx interrupt disabled
68    Disabled = 0,
69    ///1: CCx interrupt enabled
70    Enabled = 1,
71}
72impl From<CC1IE> for bool {
73    #[inline(always)]
74    fn from(variant: CC1IE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCIE(1-1)` reader - Capture/Compare %s interrupt enable
79pub type CCIE_R = crate::BitReader<CC1IE>;
80impl CCIE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1IE {
84        match self.bits {
85            false => CC1IE::Disabled,
86            true => CC1IE::Enabled,
87        }
88    }
89    ///CCx interrupt disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == CC1IE::Disabled
93    }
94    ///CCx interrupt enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == CC1IE::Enabled
98    }
99}
100///Field `CCIE(1-1)` writer - Capture/Compare %s interrupt enable
101pub type CCIE_W<'a, REG> = crate::BitWriter<'a, REG, CC1IE>;
102impl<'a, REG> CCIE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///CCx interrupt disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1IE::Disabled)
110    }
111    ///CCx interrupt enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1IE::Enabled)
115    }
116}
117impl R {
118    ///Bit 0 - Update interrupt enable
119    #[inline(always)]
120    pub fn uie(&self) -> UIE_R {
121        UIE_R::new((self.bits & 1) != 0)
122    }
123    ///Capture/Compare (1-1) interrupt enable
124    ///
125    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IE` field.</div>
126    #[inline(always)]
127    pub fn ccie(&self, n: u8) -> CCIE_R {
128        #[allow(clippy::no_effect)]
129        [(); 1][n as usize];
130        CCIE_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0)
131    }
132    ///Iterator for array of:
133    ///Capture/Compare (1-1) interrupt enable
134    #[inline(always)]
135    pub fn ccie_iter(&self) -> impl Iterator<Item = CCIE_R> + '_ {
136        (0..1).map(move |n| CCIE_R::new(((self.bits >> (n * 0 + 1)) & 1) != 0))
137    }
138    ///Bit 1 - Capture/Compare 1 interrupt enable
139    #[inline(always)]
140    pub fn cc1ie(&self) -> CCIE_R {
141        CCIE_R::new(((self.bits >> 1) & 1) != 0)
142    }
143}
144impl core::fmt::Debug for R {
145    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
146        f.debug_struct("DIER")
147            .field("uie", &self.uie())
148            .field("cc1ie", &self.cc1ie())
149            .finish()
150    }
151}
152impl W {
153    ///Bit 0 - Update interrupt enable
154    #[inline(always)]
155    pub fn uie(&mut self) -> UIE_W<DIERrs> {
156        UIE_W::new(self, 0)
157    }
158    ///Capture/Compare (1-1) interrupt enable
159    ///
160    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IE` field.</div>
161    #[inline(always)]
162    pub fn ccie(&mut self, n: u8) -> CCIE_W<DIERrs> {
163        #[allow(clippy::no_effect)]
164        [(); 1][n as usize];
165        CCIE_W::new(self, n * 0 + 1)
166    }
167    ///Bit 1 - Capture/Compare 1 interrupt enable
168    #[inline(always)]
169    pub fn cc1ie(&mut self) -> CCIE_W<DIERrs> {
170        CCIE_W::new(self, 1)
171    }
172}
173/**DMA/Interrupt enable register
174
175You can [`read`](crate::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
176
177See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM14:DIER)*/
178pub struct DIERrs;
179impl crate::RegisterSpec for DIERrs {
180    type Ux = u32;
181}
182///`read()` method returns [`dier::R`](R) reader structure
183impl crate::Readable for DIERrs {}
184///`write(|w| ..)` method takes [`dier::W`](W) writer structure
185impl crate::Writable for DIERrs {
186    type Safety = crate::Unsafe;
187}
188///`reset()` method sets DIER to value 0
189impl crate::Resettable for DIERrs {}
stm32g0/stm32g0b0/tim14/dier.rs

stm32g0/stm32g0b0/tim14/
dier.rs
