stm32g0/stm32g0b0/rcc/
ccipr.rs

1///Register `CCIPR` reader
2pub type R = crate::R<CCIPRrs>;
3///Register `CCIPR` writer
4pub type W = crate::W<CCIPRrs>;
5/**USART1 clock source selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum USART1SEL {
12    ///0: PCLK clock selected
13    Pclk = 0,
14    ///1: SYSCLK clock selected
15    Sysclk = 1,
16    ///2: HSI16 clock selected
17    Hsi16 = 2,
18    ///3: LSE clock selected
19    Lse = 3,
20}
21impl From<USART1SEL> for u8 {
22    #[inline(always)]
23    fn from(variant: USART1SEL) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for USART1SEL {
28    type Ux = u8;
29}
30impl crate::IsEnum for USART1SEL {}
31///Field `USART1SEL` reader - USART1 clock source selection
32pub type USART1SEL_R = crate::FieldReader<USART1SEL>;
33impl USART1SEL_R {
34    ///Get enumerated values variant
35    #[inline(always)]
36    pub const fn variant(&self) -> USART1SEL {
37        match self.bits {
38            0 => USART1SEL::Pclk,
39            1 => USART1SEL::Sysclk,
40            2 => USART1SEL::Hsi16,
41            3 => USART1SEL::Lse,
42            _ => unreachable!(),
43        }
44    }
45    ///PCLK clock selected
46    #[inline(always)]
47    pub fn is_pclk(&self) -> bool {
48        *self == USART1SEL::Pclk
49    }
50    ///SYSCLK clock selected
51    #[inline(always)]
52    pub fn is_sysclk(&self) -> bool {
53        *self == USART1SEL::Sysclk
54    }
55    ///HSI16 clock selected
56    #[inline(always)]
57    pub fn is_hsi16(&self) -> bool {
58        *self == USART1SEL::Hsi16
59    }
60    ///LSE clock selected
61    #[inline(always)]
62    pub fn is_lse(&self) -> bool {
63        *self == USART1SEL::Lse
64    }
65}
66///Field `USART1SEL` writer - USART1 clock source selection
67pub type USART1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, USART1SEL, crate::Safe>;
68impl<'a, REG> USART1SEL_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    ///PCLK clock selected
74    #[inline(always)]
75    pub fn pclk(self) -> &'a mut crate::W<REG> {
76        self.variant(USART1SEL::Pclk)
77    }
78    ///SYSCLK clock selected
79    #[inline(always)]
80    pub fn sysclk(self) -> &'a mut crate::W<REG> {
81        self.variant(USART1SEL::Sysclk)
82    }
83    ///HSI16 clock selected
84    #[inline(always)]
85    pub fn hsi16(self) -> &'a mut crate::W<REG> {
86        self.variant(USART1SEL::Hsi16)
87    }
88    ///LSE clock selected
89    #[inline(always)]
90    pub fn lse(self) -> &'a mut crate::W<REG> {
91        self.variant(USART1SEL::Lse)
92    }
93}
94///Field `USART2SEL` reader - USART2 clock source selection
95pub use USART1SEL_R as USART2SEL_R;
96///Field `USART3SEL` reader - USART3 clock source selection
97pub use USART1SEL_R as USART3SEL_R;
98///Field `USART2SEL` writer - USART2 clock source selection
99pub use USART1SEL_W as USART2SEL_W;
100///Field `USART3SEL` writer - USART3 clock source selection
101pub use USART1SEL_W as USART3SEL_W;
102/**I2C1 clock source selection
103
104Value on reset: 0*/
105#[cfg_attr(feature = "defmt", derive(defmt::Format))]
106#[derive(Clone, Copy, Debug, PartialEq, Eq)]
107#[repr(u8)]
108pub enum I2C1SEL {
109    ///0: PCLK clock selected
110    Pclk = 0,
111    ///1: SYSCLK clock selected
112    Sysclk = 1,
113    ///2: HSI16 clock selected
114    Hsi16 = 2,
115}
116impl From<I2C1SEL> for u8 {
117    #[inline(always)]
118    fn from(variant: I2C1SEL) -> Self {
119        variant as _
120    }
121}
122impl crate::FieldSpec for I2C1SEL {
123    type Ux = u8;
124}
125impl crate::IsEnum for I2C1SEL {}
126///Field `I2C1SEL` reader - I2C1 clock source selection
127pub type I2C1SEL_R = crate::FieldReader<I2C1SEL>;
128impl I2C1SEL_R {
129    ///Get enumerated values variant
130    #[inline(always)]
131    pub const fn variant(&self) -> Option<I2C1SEL> {
132        match self.bits {
133            0 => Some(I2C1SEL::Pclk),
134            1 => Some(I2C1SEL::Sysclk),
135            2 => Some(I2C1SEL::Hsi16),
136            _ => None,
137        }
138    }
139    ///PCLK clock selected
140    #[inline(always)]
141    pub fn is_pclk(&self) -> bool {
142        *self == I2C1SEL::Pclk
143    }
144    ///SYSCLK clock selected
145    #[inline(always)]
146    pub fn is_sysclk(&self) -> bool {
147        *self == I2C1SEL::Sysclk
148    }
149    ///HSI16 clock selected
150    #[inline(always)]
151    pub fn is_hsi16(&self) -> bool {
152        *self == I2C1SEL::Hsi16
153    }
154}
155///Field `I2C1SEL` writer - I2C1 clock source selection
156pub type I2C1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, I2C1SEL>;
157impl<'a, REG> I2C1SEL_W<'a, REG>
158where
159    REG: crate::Writable + crate::RegisterSpec,
160    REG::Ux: From<u8>,
161{
162    ///PCLK clock selected
163    #[inline(always)]
164    pub fn pclk(self) -> &'a mut crate::W<REG> {
165        self.variant(I2C1SEL::Pclk)
166    }
167    ///SYSCLK clock selected
168    #[inline(always)]
169    pub fn sysclk(self) -> &'a mut crate::W<REG> {
170        self.variant(I2C1SEL::Sysclk)
171    }
172    ///HSI16 clock selected
173    #[inline(always)]
174    pub fn hsi16(self) -> &'a mut crate::W<REG> {
175        self.variant(I2C1SEL::Hsi16)
176    }
177}
178/**I2S1 clock source selection
179
180Value on reset: 0*/
181#[cfg_attr(feature = "defmt", derive(defmt::Format))]
182#[derive(Clone, Copy, Debug, PartialEq, Eq)]
183#[repr(u8)]
184pub enum I2C2SEL {
185    ///0: PCLK clock selected
186    Pclk = 0,
187    ///1: SYSCLK clock selected
188    Sysclk = 1,
189    ///2: HSI16 clock selected
190    Hsi16 = 2,
191}
192impl From<I2C2SEL> for u8 {
193    #[inline(always)]
194    fn from(variant: I2C2SEL) -> Self {
195        variant as _
196    }
197}
198impl crate::FieldSpec for I2C2SEL {
199    type Ux = u8;
200}
201impl crate::IsEnum for I2C2SEL {}
202///Field `I2C2SEL` reader - I2S1 clock source selection
203pub type I2C2SEL_R = crate::FieldReader<I2C2SEL>;
204impl I2C2SEL_R {
205    ///Get enumerated values variant
206    #[inline(always)]
207    pub const fn variant(&self) -> Option<I2C2SEL> {
208        match self.bits {
209            0 => Some(I2C2SEL::Pclk),
210            1 => Some(I2C2SEL::Sysclk),
211            2 => Some(I2C2SEL::Hsi16),
212            _ => None,
213        }
214    }
215    ///PCLK clock selected
216    #[inline(always)]
217    pub fn is_pclk(&self) -> bool {
218        *self == I2C2SEL::Pclk
219    }
220    ///SYSCLK clock selected
221    #[inline(always)]
222    pub fn is_sysclk(&self) -> bool {
223        *self == I2C2SEL::Sysclk
224    }
225    ///HSI16 clock selected
226    #[inline(always)]
227    pub fn is_hsi16(&self) -> bool {
228        *self == I2C2SEL::Hsi16
229    }
230}
231///Field `I2C2SEL` writer - I2S1 clock source selection
232pub type I2C2SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, I2C2SEL>;
233impl<'a, REG> I2C2SEL_W<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236    REG::Ux: From<u8>,
237{
238    ///PCLK clock selected
239    #[inline(always)]
240    pub fn pclk(self) -> &'a mut crate::W<REG> {
241        self.variant(I2C2SEL::Pclk)
242    }
243    ///SYSCLK clock selected
244    #[inline(always)]
245    pub fn sysclk(self) -> &'a mut crate::W<REG> {
246        self.variant(I2C2SEL::Sysclk)
247    }
248    ///HSI16 clock selected
249    #[inline(always)]
250    pub fn hsi16(self) -> &'a mut crate::W<REG> {
251        self.variant(I2C2SEL::Hsi16)
252    }
253}
254/**TIM1 clock source selection
255
256Value on reset: 0*/
257#[cfg_attr(feature = "defmt", derive(defmt::Format))]
258#[derive(Clone, Copy, Debug, PartialEq, Eq)]
259pub enum TIM1SEL {
260    ///0: TIMPCLK clock selected
261    Timp = 0,
262    ///1: PLLQCLK clock selected
263    Pllq = 1,
264}
265impl From<TIM1SEL> for bool {
266    #[inline(always)]
267    fn from(variant: TIM1SEL) -> Self {
268        variant as u8 != 0
269    }
270}
271///Field `TIM1SEL` reader - TIM1 clock source selection
272pub type TIM1SEL_R = crate::BitReader<TIM1SEL>;
273impl TIM1SEL_R {
274    ///Get enumerated values variant
275    #[inline(always)]
276    pub const fn variant(&self) -> TIM1SEL {
277        match self.bits {
278            false => TIM1SEL::Timp,
279            true => TIM1SEL::Pllq,
280        }
281    }
282    ///TIMPCLK clock selected
283    #[inline(always)]
284    pub fn is_timp(&self) -> bool {
285        *self == TIM1SEL::Timp
286    }
287    ///PLLQCLK clock selected
288    #[inline(always)]
289    pub fn is_pllq(&self) -> bool {
290        *self == TIM1SEL::Pllq
291    }
292}
293///Field `TIM1SEL` writer - TIM1 clock source selection
294pub type TIM1SEL_W<'a, REG> = crate::BitWriter<'a, REG, TIM1SEL>;
295impl<'a, REG> TIM1SEL_W<'a, REG>
296where
297    REG: crate::Writable + crate::RegisterSpec,
298{
299    ///TIMPCLK clock selected
300    #[inline(always)]
301    pub fn timp(self) -> &'a mut crate::W<REG> {
302        self.variant(TIM1SEL::Timp)
303    }
304    ///PLLQCLK clock selected
305    #[inline(always)]
306    pub fn pllq(self) -> &'a mut crate::W<REG> {
307        self.variant(TIM1SEL::Pllq)
308    }
309}
310///Field `TIM15SEL` reader - TIM15 clock source selection
311pub use TIM1SEL_R as TIM15SEL_R;
312///Field `TIM15SEL` writer - TIM15 clock source selection
313pub use TIM1SEL_W as TIM15SEL_W;
314/**ADCs clock source selection
315
316Value on reset: 0*/
317#[cfg_attr(feature = "defmt", derive(defmt::Format))]
318#[derive(Clone, Copy, Debug, PartialEq, Eq)]
319#[repr(u8)]
320pub enum ADCSEL {
321    ///0: System clock selected
322    Sysclk = 0,
323    ///1: PLLPCLK clock selected
324    Pllp = 1,
325    ///2: HSI16 clock selected
326    Hsi16 = 2,
327}
328impl From<ADCSEL> for u8 {
329    #[inline(always)]
330    fn from(variant: ADCSEL) -> Self {
331        variant as _
332    }
333}
334impl crate::FieldSpec for ADCSEL {
335    type Ux = u8;
336}
337impl crate::IsEnum for ADCSEL {}
338///Field `ADCSEL` reader - ADCs clock source selection
339pub type ADCSEL_R = crate::FieldReader<ADCSEL>;
340impl ADCSEL_R {
341    ///Get enumerated values variant
342    #[inline(always)]
343    pub const fn variant(&self) -> Option<ADCSEL> {
344        match self.bits {
345            0 => Some(ADCSEL::Sysclk),
346            1 => Some(ADCSEL::Pllp),
347            2 => Some(ADCSEL::Hsi16),
348            _ => None,
349        }
350    }
351    ///System clock selected
352    #[inline(always)]
353    pub fn is_sysclk(&self) -> bool {
354        *self == ADCSEL::Sysclk
355    }
356    ///PLLPCLK clock selected
357    #[inline(always)]
358    pub fn is_pllp(&self) -> bool {
359        *self == ADCSEL::Pllp
360    }
361    ///HSI16 clock selected
362    #[inline(always)]
363    pub fn is_hsi16(&self) -> bool {
364        *self == ADCSEL::Hsi16
365    }
366}
367///Field `ADCSEL` writer - ADCs clock source selection
368pub type ADCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ADCSEL>;
369impl<'a, REG> ADCSEL_W<'a, REG>
370where
371    REG: crate::Writable + crate::RegisterSpec,
372    REG::Ux: From<u8>,
373{
374    ///System clock selected
375    #[inline(always)]
376    pub fn sysclk(self) -> &'a mut crate::W<REG> {
377        self.variant(ADCSEL::Sysclk)
378    }
379    ///PLLPCLK clock selected
380    #[inline(always)]
381    pub fn pllp(self) -> &'a mut crate::W<REG> {
382        self.variant(ADCSEL::Pllp)
383    }
384    ///HSI16 clock selected
385    #[inline(always)]
386    pub fn hsi16(self) -> &'a mut crate::W<REG> {
387        self.variant(ADCSEL::Hsi16)
388    }
389}
390impl R {
391    ///Bits 0:1 - USART1 clock source selection
392    #[inline(always)]
393    pub fn usart1sel(&self) -> USART1SEL_R {
394        USART1SEL_R::new((self.bits & 3) as u8)
395    }
396    ///Bits 2:3 - USART2 clock source selection
397    #[inline(always)]
398    pub fn usart2sel(&self) -> USART2SEL_R {
399        USART2SEL_R::new(((self.bits >> 2) & 3) as u8)
400    }
401    ///Bits 4:5 - USART3 clock source selection
402    #[inline(always)]
403    pub fn usart3sel(&self) -> USART3SEL_R {
404        USART3SEL_R::new(((self.bits >> 4) & 3) as u8)
405    }
406    ///Bits 12:13 - I2C1 clock source selection
407    #[inline(always)]
408    pub fn i2c1sel(&self) -> I2C1SEL_R {
409        I2C1SEL_R::new(((self.bits >> 12) & 3) as u8)
410    }
411    ///Bits 14:15 - I2S1 clock source selection
412    #[inline(always)]
413    pub fn i2c2sel(&self) -> I2C2SEL_R {
414        I2C2SEL_R::new(((self.bits >> 14) & 3) as u8)
415    }
416    ///Bit 22 - TIM1 clock source selection
417    #[inline(always)]
418    pub fn tim1sel(&self) -> TIM1SEL_R {
419        TIM1SEL_R::new(((self.bits >> 22) & 1) != 0)
420    }
421    ///Bit 24 - TIM15 clock source selection
422    #[inline(always)]
423    pub fn tim15sel(&self) -> TIM15SEL_R {
424        TIM15SEL_R::new(((self.bits >> 24) & 1) != 0)
425    }
426    ///Bits 30:31 - ADCs clock source selection
427    #[inline(always)]
428    pub fn adcsel(&self) -> ADCSEL_R {
429        ADCSEL_R::new(((self.bits >> 30) & 3) as u8)
430    }
431}
432impl core::fmt::Debug for R {
433    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
434        f.debug_struct("CCIPR")
435            .field("usart1sel", &self.usart1sel())
436            .field("usart2sel", &self.usart2sel())
437            .field("usart3sel", &self.usart3sel())
438            .field("i2c1sel", &self.i2c1sel())
439            .field("i2c2sel", &self.i2c2sel())
440            .field("tim1sel", &self.tim1sel())
441            .field("tim15sel", &self.tim15sel())
442            .field("adcsel", &self.adcsel())
443            .finish()
444    }
445}
446impl W {
447    ///Bits 0:1 - USART1 clock source selection
448    #[inline(always)]
449    pub fn usart1sel(&mut self) -> USART1SEL_W<CCIPRrs> {
450        USART1SEL_W::new(self, 0)
451    }
452    ///Bits 2:3 - USART2 clock source selection
453    #[inline(always)]
454    pub fn usart2sel(&mut self) -> USART2SEL_W<CCIPRrs> {
455        USART2SEL_W::new(self, 2)
456    }
457    ///Bits 4:5 - USART3 clock source selection
458    #[inline(always)]
459    pub fn usart3sel(&mut self) -> USART3SEL_W<CCIPRrs> {
460        USART3SEL_W::new(self, 4)
461    }
462    ///Bits 12:13 - I2C1 clock source selection
463    #[inline(always)]
464    pub fn i2c1sel(&mut self) -> I2C1SEL_W<CCIPRrs> {
465        I2C1SEL_W::new(self, 12)
466    }
467    ///Bits 14:15 - I2S1 clock source selection
468    #[inline(always)]
469    pub fn i2c2sel(&mut self) -> I2C2SEL_W<CCIPRrs> {
470        I2C2SEL_W::new(self, 14)
471    }
472    ///Bit 22 - TIM1 clock source selection
473    #[inline(always)]
474    pub fn tim1sel(&mut self) -> TIM1SEL_W<CCIPRrs> {
475        TIM1SEL_W::new(self, 22)
476    }
477    ///Bit 24 - TIM15 clock source selection
478    #[inline(always)]
479    pub fn tim15sel(&mut self) -> TIM15SEL_W<CCIPRrs> {
480        TIM15SEL_W::new(self, 24)
481    }
482    ///Bits 30:31 - ADCs clock source selection
483    #[inline(always)]
484    pub fn adcsel(&mut self) -> ADCSEL_W<CCIPRrs> {
485        ADCSEL_W::new(self, 30)
486    }
487}
488/**Peripherals independent clock configuration register
489
490You can [`read`](crate::Reg::read) this register and get [`ccipr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
491
492See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CCIPR)*/
493pub struct CCIPRrs;
494impl crate::RegisterSpec for CCIPRrs {
495    type Ux = u32;
496}
497///`read()` method returns [`ccipr::R`](R) reader structure
498impl crate::Readable for CCIPRrs {}
499///`write(|w| ..)` method takes [`ccipr::W`](W) writer structure
500impl crate::Writable for CCIPRrs {
501    type Safety = crate::Unsafe;
502}
503///`reset()` method sets CCIPR to value 0
504impl crate::Resettable for CCIPRrs {}
stm32g0/stm32g0b0/rcc/ccipr.rs

stm32g0/stm32g0b0/rcc/
ccipr.rs
