stm32g0/stm32g0b0/gpioa/
brr.rs

1///Register `BRR` writer
2pub type W = crate::W<BRRrs>;
3/**Port x reset pin %s
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum BIT_RESET {
9    ///0: No action on the corresponding ODx bit
10    NoAction = 0,
11    ///1: Reset the ODx bit
12    Reset = 1,
13}
14impl From<BIT_RESET> for bool {
15    #[inline(always)]
16    fn from(variant: BIT_RESET) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `BR(0-15)` writer - Port x reset pin %s
21pub type BR_W<'a, REG> = crate::BitWriter<'a, REG, BIT_RESET>;
22impl<'a, REG> BR_W<'a, REG>
23where
24    REG: crate::Writable + crate::RegisterSpec,
25{
26    ///No action on the corresponding ODx bit
27    #[inline(always)]
28    pub fn no_action(self) -> &'a mut crate::W<REG> {
29        self.variant(BIT_RESET::NoAction)
30    }
31    ///Reset the ODx bit
32    #[inline(always)]
33    pub fn reset(self) -> &'a mut crate::W<REG> {
34        self.variant(BIT_RESET::Reset)
35    }
36}
37impl core::fmt::Debug for crate::generic::Reg<BRRrs> {
38    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
39        write!(f, "(not readable)")
40    }
41}
42impl W {
43    ///Port x reset pin (0-15)
44    ///
45    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BR0` field.</div>
46    #[inline(always)]
47    pub fn br(&mut self, n: u8) -> BR_W<BRRrs> {
48        #[allow(clippy::no_effect)]
49        [(); 16][n as usize];
50        BR_W::new(self, n)
51    }
52    ///Bit 0 - Port x reset pin 0
53    #[inline(always)]
54    pub fn br0(&mut self) -> BR_W<BRRrs> {
55        BR_W::new(self, 0)
56    }
57    ///Bit 1 - Port x reset pin 1
58    #[inline(always)]
59    pub fn br1(&mut self) -> BR_W<BRRrs> {
60        BR_W::new(self, 1)
61    }
62    ///Bit 2 - Port x reset pin 2
63    #[inline(always)]
64    pub fn br2(&mut self) -> BR_W<BRRrs> {
65        BR_W::new(self, 2)
66    }
67    ///Bit 3 - Port x reset pin 3
68    #[inline(always)]
69    pub fn br3(&mut self) -> BR_W<BRRrs> {
70        BR_W::new(self, 3)
71    }
72    ///Bit 4 - Port x reset pin 4
73    #[inline(always)]
74    pub fn br4(&mut self) -> BR_W<BRRrs> {
75        BR_W::new(self, 4)
76    }
77    ///Bit 5 - Port x reset pin 5
78    #[inline(always)]
79    pub fn br5(&mut self) -> BR_W<BRRrs> {
80        BR_W::new(self, 5)
81    }
82    ///Bit 6 - Port x reset pin 6
83    #[inline(always)]
84    pub fn br6(&mut self) -> BR_W<BRRrs> {
85        BR_W::new(self, 6)
86    }
87    ///Bit 7 - Port x reset pin 7
88    #[inline(always)]
89    pub fn br7(&mut self) -> BR_W<BRRrs> {
90        BR_W::new(self, 7)
91    }
92    ///Bit 8 - Port x reset pin 8
93    #[inline(always)]
94    pub fn br8(&mut self) -> BR_W<BRRrs> {
95        BR_W::new(self, 8)
96    }
97    ///Bit 9 - Port x reset pin 9
98    #[inline(always)]
99    pub fn br9(&mut self) -> BR_W<BRRrs> {
100        BR_W::new(self, 9)
101    }
102    ///Bit 10 - Port x reset pin 10
103    #[inline(always)]
104    pub fn br10(&mut self) -> BR_W<BRRrs> {
105        BR_W::new(self, 10)
106    }
107    ///Bit 11 - Port x reset pin 11
108    #[inline(always)]
109    pub fn br11(&mut self) -> BR_W<BRRrs> {
110        BR_W::new(self, 11)
111    }
112    ///Bit 12 - Port x reset pin 12
113    #[inline(always)]
114    pub fn br12(&mut self) -> BR_W<BRRrs> {
115        BR_W::new(self, 12)
116    }
117    ///Bit 13 - Port x reset pin 13
118    #[inline(always)]
119    pub fn br13(&mut self) -> BR_W<BRRrs> {
120        BR_W::new(self, 13)
121    }
122    ///Bit 14 - Port x reset pin 14
123    #[inline(always)]
124    pub fn br14(&mut self) -> BR_W<BRRrs> {
125        BR_W::new(self, 14)
126    }
127    ///Bit 15 - Port x reset pin 15
128    #[inline(always)]
129    pub fn br15(&mut self) -> BR_W<BRRrs> {
130        BR_W::new(self, 15)
131    }
132}
133/**port bit reset register
134
135You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
136
137See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#GPIOA:BRR)*/
138pub struct BRRrs;
139impl crate::RegisterSpec for BRRrs {
140    type Ux = u32;
141}
142///`write(|w| ..)` method takes [`brr::W`](W) writer structure
143impl crate::Writable for BRRrs {
144    type Safety = crate::Unsafe;
145}
146///`reset()` method sets BRR to value 0
147impl crate::Resettable for BRRrs {}
stm32g0/stm32g0b0/gpioa/brr.rs

stm32g0/stm32g0b0/gpioa/
brr.rs
