stm32g0/stm32g081/tim15/
tisel.rs

1///Register `TISEL` reader
2pub type R = crate::R<TISELrs>;
3///Register `TISEL` writer
4pub type W = crate::W<TISELrs>;
5///Field `TI1SEL` reader - selects TI1\[0\] to TI1\[15\] input Others: Reserved
6pub type TI1SEL_R = crate::FieldReader;
7///Field `TI1SEL` writer - selects TI1\[0\] to TI1\[15\] input Others: Reserved
8pub type TI1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9///Field `TI2SEL` reader - selects TI2\[0\] to TI2\[15\] input Others: Reserved
10pub type TI2SEL_R = crate::FieldReader;
11///Field `TI2SEL` writer - selects TI2\[0\] to TI2\[15\] input Others: Reserved
12pub type TI2SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    ///Bits 0:3 - selects TI1\[0\] to TI1\[15\] input Others: Reserved
15    #[inline(always)]
16    pub fn ti1sel(&self) -> TI1SEL_R {
17        TI1SEL_R::new((self.bits & 0x0f) as u8)
18    }
19    ///Bits 8:11 - selects TI2\[0\] to TI2\[15\] input Others: Reserved
20    #[inline(always)]
21    pub fn ti2sel(&self) -> TI2SEL_R {
22        TI2SEL_R::new(((self.bits >> 8) & 0x0f) as u8)
23    }
24}
25impl core::fmt::Debug for R {
26    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27        f.debug_struct("TISEL")
28            .field("ti1sel", &self.ti1sel())
29            .field("ti2sel", &self.ti2sel())
30            .finish()
31    }
32}
33impl W {
34    ///Bits 0:3 - selects TI1\[0\] to TI1\[15\] input Others: Reserved
35    #[inline(always)]
36    pub fn ti1sel(&mut self) -> TI1SEL_W<TISELrs> {
37        TI1SEL_W::new(self, 0)
38    }
39    ///Bits 8:11 - selects TI2\[0\] to TI2\[15\] input Others: Reserved
40    #[inline(always)]
41    pub fn ti2sel(&mut self) -> TI2SEL_W<TISELrs> {
42        TI2SEL_W::new(self, 8)
43    }
44}
45/**input selection register
46
47You can [`read`](crate::Reg::read) this register and get [`tisel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
48
49See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#TIM15:TISEL)*/
50pub struct TISELrs;
51impl crate::RegisterSpec for TISELrs {
52    type Ux = u32;
53}
54///`read()` method returns [`tisel::R`](R) reader structure
55impl crate::Readable for TISELrs {}
56///`write(|w| ..)` method takes [`tisel::W`](W) writer structure
57impl crate::Writable for TISELrs {
58    type Safety = crate::Unsafe;
59}
60///`reset()` method sets TISEL to value 0
61impl crate::Resettable for TISELrs {}
stm32g0/stm32g081/tim15/tisel.rs

stm32g0/stm32g081/tim15/
tisel.rs
