stm32g0/stm32g070/tim1/
ccmr2_output.rs

1///Register `CCMR2_Output` reader
2pub type R = crate::R<CCMR2_OUTPUTrs>;
3///Register `CCMR2_Output` writer
4pub type W = crate::W<CCMR2_OUTPUTrs>;
5///Capture/Compare %s selection
6pub use super::ccmr1_output::CC1S;
7///Field `CCS(3-4)` reader - Capture/Compare %s selection
8pub use super::ccmr1_output::CCS_R;
9///Field `CCS(3-4)` writer - Capture/Compare %s selection
10pub use super::ccmr1_output::CCS_W;
11///Output compare %s clear enable
12pub use super::ccmr1_output::OC1CE;
13///Output compare %s fast enable
14pub use super::ccmr1_output::OC1FE;
15///Output compare %s mode
16pub use super::ccmr1_output::OC1M;
17///Output compare %s mode, bit 3
18pub use super::ccmr1_output::OC1M_3;
19///Output compare %s preload enable
20pub use super::ccmr1_output::OC1PE;
21///Field `OCCE(3-4)` reader - Output compare %s clear enable
22pub use super::ccmr1_output::OCCE_R;
23///Field `OCCE(3-4)` writer - Output compare %s clear enable
24pub use super::ccmr1_output::OCCE_W;
25///Field `OCFE(3-4)` reader - Output compare %s fast enable
26pub use super::ccmr1_output::OCFE_R;
27///Field `OCFE(3-4)` writer - Output compare %s fast enable
28pub use super::ccmr1_output::OCFE_W;
29///Field `OCM_3(3-4)` reader - Output compare %s mode, bit 3
30pub use super::ccmr1_output::OCM_3_R;
31///Field `OCM_3(3-4)` writer - Output compare %s mode, bit 3
32pub use super::ccmr1_output::OCM_3_W;
33///Field `OCM(3-4)` reader - Output compare %s mode
34pub use super::ccmr1_output::OCM_R;
35///Field `OCM(3-4)` writer - Output compare %s mode
36pub use super::ccmr1_output::OCM_W;
37///Field `OCPE(3-4)` reader - Output compare %s preload enable
38pub use super::ccmr1_output::OCPE_R;
39///Field `OCPE(3-4)` writer - Output compare %s preload enable
40pub use super::ccmr1_output::OCPE_W;
41impl R {
42    ///Capture/Compare (3-4) selection
43    ///
44    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC3S` field.</div>
45    #[inline(always)]
46    pub fn ccs(&self, n: u8) -> CCS_R {
47        #[allow(clippy::no_effect)]
48        [(); 2][n as usize];
49        CCS_R::new(((self.bits >> (n * 8)) & 3) as u8)
50    }
51    ///Iterator for array of:
52    ///Capture/Compare (3-4) selection
53    #[inline(always)]
54    pub fn ccs_iter(&self) -> impl Iterator<Item = CCS_R> + '_ {
55        (0..2).map(move |n| CCS_R::new(((self.bits >> (n * 8)) & 3) as u8))
56    }
57    ///Bits 0:1 - Capture/Compare 3 selection
58    #[inline(always)]
59    pub fn cc3s(&self) -> CCS_R {
60        CCS_R::new((self.bits & 3) as u8)
61    }
62    ///Bits 8:9 - Capture/Compare 4 selection
63    #[inline(always)]
64    pub fn cc4s(&self) -> CCS_R {
65        CCS_R::new(((self.bits >> 8) & 3) as u8)
66    }
67    ///Output compare (3-4) fast enable
68    ///
69    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3FE` field.</div>
70    #[inline(always)]
71    pub fn ocfe(&self, n: u8) -> OCFE_R {
72        #[allow(clippy::no_effect)]
73        [(); 2][n as usize];
74        OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0)
75    }
76    ///Iterator for array of:
77    ///Output compare (3-4) fast enable
78    #[inline(always)]
79    pub fn ocfe_iter(&self) -> impl Iterator<Item = OCFE_R> + '_ {
80        (0..2).map(move |n| OCFE_R::new(((self.bits >> (n * 8 + 2)) & 1) != 0))
81    }
82    ///Bit 2 - Output compare 3 fast enable
83    #[inline(always)]
84    pub fn oc3fe(&self) -> OCFE_R {
85        OCFE_R::new(((self.bits >> 2) & 1) != 0)
86    }
87    ///Bit 10 - Output compare 4 fast enable
88    #[inline(always)]
89    pub fn oc4fe(&self) -> OCFE_R {
90        OCFE_R::new(((self.bits >> 10) & 1) != 0)
91    }
92    ///Output compare (3-4) preload enable
93    ///
94    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3PE` field.</div>
95    #[inline(always)]
96    pub fn ocpe(&self, n: u8) -> OCPE_R {
97        #[allow(clippy::no_effect)]
98        [(); 2][n as usize];
99        OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0)
100    }
101    ///Iterator for array of:
102    ///Output compare (3-4) preload enable
103    #[inline(always)]
104    pub fn ocpe_iter(&self) -> impl Iterator<Item = OCPE_R> + '_ {
105        (0..2).map(move |n| OCPE_R::new(((self.bits >> (n * 8 + 3)) & 1) != 0))
106    }
107    ///Bit 3 - Output compare 3 preload enable
108    #[inline(always)]
109    pub fn oc3pe(&self) -> OCPE_R {
110        OCPE_R::new(((self.bits >> 3) & 1) != 0)
111    }
112    ///Bit 11 - Output compare 4 preload enable
113    #[inline(always)]
114    pub fn oc4pe(&self) -> OCPE_R {
115        OCPE_R::new(((self.bits >> 11) & 1) != 0)
116    }
117    ///Output compare (3-4) mode
118    ///
119    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3M` field.</div>
120    #[inline(always)]
121    pub fn ocm(&self, n: u8) -> OCM_R {
122        #[allow(clippy::no_effect)]
123        [(); 2][n as usize];
124        OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8)
125    }
126    ///Iterator for array of:
127    ///Output compare (3-4) mode
128    #[inline(always)]
129    pub fn ocm_iter(&self) -> impl Iterator<Item = OCM_R> + '_ {
130        (0..2).map(move |n| OCM_R::new(((self.bits >> (n * 8 + 4)) & 7) as u8))
131    }
132    ///Bits 4:6 - Output compare 3 mode
133    #[inline(always)]
134    pub fn oc3m(&self) -> OCM_R {
135        OCM_R::new(((self.bits >> 4) & 7) as u8)
136    }
137    ///Bits 12:14 - Output compare 4 mode
138    #[inline(always)]
139    pub fn oc4m(&self) -> OCM_R {
140        OCM_R::new(((self.bits >> 12) & 7) as u8)
141    }
142    ///Output compare (3-4) clear enable
143    ///
144    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3CE` field.</div>
145    #[inline(always)]
146    pub fn occe(&self, n: u8) -> OCCE_R {
147        #[allow(clippy::no_effect)]
148        [(); 2][n as usize];
149        OCCE_R::new(((self.bits >> (n * 8 + 7)) & 1) != 0)
150    }
151    ///Iterator for array of:
152    ///Output compare (3-4) clear enable
153    #[inline(always)]
154    pub fn occe_iter(&self) -> impl Iterator<Item = OCCE_R> + '_ {
155        (0..2).map(move |n| OCCE_R::new(((self.bits >> (n * 8 + 7)) & 1) != 0))
156    }
157    ///Bit 7 - Output compare 3 clear enable
158    #[inline(always)]
159    pub fn oc3ce(&self) -> OCCE_R {
160        OCCE_R::new(((self.bits >> 7) & 1) != 0)
161    }
162    ///Bit 15 - Output compare 4 clear enable
163    #[inline(always)]
164    pub fn oc4ce(&self) -> OCCE_R {
165        OCCE_R::new(((self.bits >> 15) & 1) != 0)
166    }
167    ///Output compare (3-4) mode, bit 3
168    ///
169    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3M_3` field.</div>
170    #[inline(always)]
171    pub fn ocm_3(&self, n: u8) -> OCM_3_R {
172        #[allow(clippy::no_effect)]
173        [(); 2][n as usize];
174        OCM_3_R::new(((self.bits >> (n * 8 + 16)) & 1) != 0)
175    }
176    ///Iterator for array of:
177    ///Output compare (3-4) mode, bit 3
178    #[inline(always)]
179    pub fn ocm_3_iter(&self) -> impl Iterator<Item = OCM_3_R> + '_ {
180        (0..2).map(move |n| OCM_3_R::new(((self.bits >> (n * 8 + 16)) & 1) != 0))
181    }
182    ///Bit 16 - Output compare 3 mode, bit 3
183    #[inline(always)]
184    pub fn oc3m_3(&self) -> OCM_3_R {
185        OCM_3_R::new(((self.bits >> 16) & 1) != 0)
186    }
187    ///Bit 24 - Output compare 4 mode, bit 3
188    #[inline(always)]
189    pub fn oc4m_3(&self) -> OCM_3_R {
190        OCM_3_R::new(((self.bits >> 24) & 1) != 0)
191    }
192}
193impl core::fmt::Debug for R {
194    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
195        f.debug_struct("CCMR2_Output")
196            .field("cc3s", &self.cc3s())
197            .field("cc4s", &self.cc4s())
198            .field("oc3fe", &self.oc3fe())
199            .field("oc4fe", &self.oc4fe())
200            .field("oc3pe", &self.oc3pe())
201            .field("oc4pe", &self.oc4pe())
202            .field("oc3m", &self.oc3m())
203            .field("oc4m", &self.oc4m())
204            .field("oc3ce", &self.oc3ce())
205            .field("oc4ce", &self.oc4ce())
206            .field("oc3m_3", &self.oc3m_3())
207            .field("oc4m_3", &self.oc4m_3())
208            .finish()
209    }
210}
211impl W {
212    ///Capture/Compare (3-4) selection
213    ///
214    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC3S` field.</div>
215    #[inline(always)]
216    pub fn ccs(&mut self, n: u8) -> CCS_W<CCMR2_OUTPUTrs> {
217        #[allow(clippy::no_effect)]
218        [(); 2][n as usize];
219        CCS_W::new(self, n * 8)
220    }
221    ///Bits 0:1 - Capture/Compare 3 selection
222    #[inline(always)]
223    pub fn cc3s(&mut self) -> CCS_W<CCMR2_OUTPUTrs> {
224        CCS_W::new(self, 0)
225    }
226    ///Bits 8:9 - Capture/Compare 4 selection
227    #[inline(always)]
228    pub fn cc4s(&mut self) -> CCS_W<CCMR2_OUTPUTrs> {
229        CCS_W::new(self, 8)
230    }
231    ///Output compare (3-4) fast enable
232    ///
233    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3FE` field.</div>
234    #[inline(always)]
235    pub fn ocfe(&mut self, n: u8) -> OCFE_W<CCMR2_OUTPUTrs> {
236        #[allow(clippy::no_effect)]
237        [(); 2][n as usize];
238        OCFE_W::new(self, n * 8 + 2)
239    }
240    ///Bit 2 - Output compare 3 fast enable
241    #[inline(always)]
242    pub fn oc3fe(&mut self) -> OCFE_W<CCMR2_OUTPUTrs> {
243        OCFE_W::new(self, 2)
244    }
245    ///Bit 10 - Output compare 4 fast enable
246    #[inline(always)]
247    pub fn oc4fe(&mut self) -> OCFE_W<CCMR2_OUTPUTrs> {
248        OCFE_W::new(self, 10)
249    }
250    ///Output compare (3-4) preload enable
251    ///
252    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3PE` field.</div>
253    #[inline(always)]
254    pub fn ocpe(&mut self, n: u8) -> OCPE_W<CCMR2_OUTPUTrs> {
255        #[allow(clippy::no_effect)]
256        [(); 2][n as usize];
257        OCPE_W::new(self, n * 8 + 3)
258    }
259    ///Bit 3 - Output compare 3 preload enable
260    #[inline(always)]
261    pub fn oc3pe(&mut self) -> OCPE_W<CCMR2_OUTPUTrs> {
262        OCPE_W::new(self, 3)
263    }
264    ///Bit 11 - Output compare 4 preload enable
265    #[inline(always)]
266    pub fn oc4pe(&mut self) -> OCPE_W<CCMR2_OUTPUTrs> {
267        OCPE_W::new(self, 11)
268    }
269    ///Output compare (3-4) mode
270    ///
271    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3M` field.</div>
272    #[inline(always)]
273    pub fn ocm(&mut self, n: u8) -> OCM_W<CCMR2_OUTPUTrs> {
274        #[allow(clippy::no_effect)]
275        [(); 2][n as usize];
276        OCM_W::new(self, n * 8 + 4)
277    }
278    ///Bits 4:6 - Output compare 3 mode
279    #[inline(always)]
280    pub fn oc3m(&mut self) -> OCM_W<CCMR2_OUTPUTrs> {
281        OCM_W::new(self, 4)
282    }
283    ///Bits 12:14 - Output compare 4 mode
284    #[inline(always)]
285    pub fn oc4m(&mut self) -> OCM_W<CCMR2_OUTPUTrs> {
286        OCM_W::new(self, 12)
287    }
288    ///Output compare (3-4) clear enable
289    ///
290    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3CE` field.</div>
291    #[inline(always)]
292    pub fn occe(&mut self, n: u8) -> OCCE_W<CCMR2_OUTPUTrs> {
293        #[allow(clippy::no_effect)]
294        [(); 2][n as usize];
295        OCCE_W::new(self, n * 8 + 7)
296    }
297    ///Bit 7 - Output compare 3 clear enable
298    #[inline(always)]
299    pub fn oc3ce(&mut self) -> OCCE_W<CCMR2_OUTPUTrs> {
300        OCCE_W::new(self, 7)
301    }
302    ///Bit 15 - Output compare 4 clear enable
303    #[inline(always)]
304    pub fn oc4ce(&mut self) -> OCCE_W<CCMR2_OUTPUTrs> {
305        OCCE_W::new(self, 15)
306    }
307    ///Output compare (3-4) mode, bit 3
308    ///
309    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC3M_3` field.</div>
310    #[inline(always)]
311    pub fn ocm_3(&mut self, n: u8) -> OCM_3_W<CCMR2_OUTPUTrs> {
312        #[allow(clippy::no_effect)]
313        [(); 2][n as usize];
314        OCM_3_W::new(self, n * 8 + 16)
315    }
316    ///Bit 16 - Output compare 3 mode, bit 3
317    #[inline(always)]
318    pub fn oc3m_3(&mut self) -> OCM_3_W<CCMR2_OUTPUTrs> {
319        OCM_3_W::new(self, 16)
320    }
321    ///Bit 24 - Output compare 4 mode, bit 3
322    #[inline(always)]
323    pub fn oc4m_3(&mut self) -> OCM_3_W<CCMR2_OUTPUTrs> {
324        OCM_3_W::new(self, 24)
325    }
326}
327/**capture/compare mode register 2 (output mode)
328
329You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
330
331See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G070.html#TIM1:CCMR2_Output)*/
332pub struct CCMR2_OUTPUTrs;
333impl crate::RegisterSpec for CCMR2_OUTPUTrs {
334    type Ux = u32;
335}
336///`read()` method returns [`ccmr2_output::R`](R) reader structure
337impl crate::Readable for CCMR2_OUTPUTrs {}
338///`write(|w| ..)` method takes [`ccmr2_output::W`](W) writer structure
339impl crate::Writable for CCMR2_OUTPUTrs {
340    type Safety = crate::Unsafe;
341}
342///`reset()` method sets CCMR2_Output to value 0
343impl crate::Resettable for CCMR2_OUTPUTrs {}
stm32g0/stm32g070/tim1/ccmr2_output.rs

stm32g0/stm32g070/tim1/
ccmr2_output.rs
