stm32g0/stm32g041/rtc/
icsr.rs

1///Register `ICSR` reader
2pub type R = crate::R<ICSRrs>;
3///Register `ICSR` writer
4pub type W = crate::W<ICSRrs>;
5///Field `ALRWF(A,B)` reader - Alarm %s write flag
6pub type ALRWF_R = crate::BitReader;
7/**Wakeup timer write flag
8
9Value on reset: 1*/
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum WUTWFR {
13    ///0: Wakeup timer configuration update not allowed
14    UpdateNotAllowed = 0,
15    ///1: Wakeup timer configuration update allowed
16    UpdateAllowed = 1,
17}
18impl From<WUTWFR> for bool {
19    #[inline(always)]
20    fn from(variant: WUTWFR) -> Self {
21        variant as u8 != 0
22    }
23}
24///Field `WUTWF` reader - Wakeup timer write flag
25pub type WUTWF_R = crate::BitReader<WUTWFR>;
26impl WUTWF_R {
27    ///Get enumerated values variant
28    #[inline(always)]
29    pub const fn variant(&self) -> WUTWFR {
30        match self.bits {
31            false => WUTWFR::UpdateNotAllowed,
32            true => WUTWFR::UpdateAllowed,
33        }
34    }
35    ///Wakeup timer configuration update not allowed
36    #[inline(always)]
37    pub fn is_update_not_allowed(&self) -> bool {
38        *self == WUTWFR::UpdateNotAllowed
39    }
40    ///Wakeup timer configuration update allowed
41    #[inline(always)]
42    pub fn is_update_allowed(&self) -> bool {
43        *self == WUTWFR::UpdateAllowed
44    }
45}
46/**Shift operation pending
47
48Value on reset: 0*/
49#[cfg_attr(feature = "defmt", derive(defmt::Format))]
50#[derive(Clone, Copy, Debug, PartialEq, Eq)]
51pub enum SHPFR {
52    ///0: No shift operation is pending
53    NoShiftPending = 0,
54    ///1: A shift operation is pending
55    ShiftPending = 1,
56}
57impl From<SHPFR> for bool {
58    #[inline(always)]
59    fn from(variant: SHPFR) -> Self {
60        variant as u8 != 0
61    }
62}
63///Field `SHPF` reader - Shift operation pending
64pub type SHPF_R = crate::BitReader<SHPFR>;
65impl SHPF_R {
66    ///Get enumerated values variant
67    #[inline(always)]
68    pub const fn variant(&self) -> SHPFR {
69        match self.bits {
70            false => SHPFR::NoShiftPending,
71            true => SHPFR::ShiftPending,
72        }
73    }
74    ///No shift operation is pending
75    #[inline(always)]
76    pub fn is_no_shift_pending(&self) -> bool {
77        *self == SHPFR::NoShiftPending
78    }
79    ///A shift operation is pending
80    #[inline(always)]
81    pub fn is_shift_pending(&self) -> bool {
82        *self == SHPFR::ShiftPending
83    }
84}
85///Field `SHPF` writer - Shift operation pending
86pub type SHPF_W<'a, REG> = crate::BitWriter<'a, REG, SHPFR>;
87impl<'a, REG> SHPF_W<'a, REG>
88where
89    REG: crate::Writable + crate::RegisterSpec,
90{
91    ///No shift operation is pending
92    #[inline(always)]
93    pub fn no_shift_pending(self) -> &'a mut crate::W<REG> {
94        self.variant(SHPFR::NoShiftPending)
95    }
96    ///A shift operation is pending
97    #[inline(always)]
98    pub fn shift_pending(self) -> &'a mut crate::W<REG> {
99        self.variant(SHPFR::ShiftPending)
100    }
101}
102/**Initialization status flag
103
104Value on reset: 0*/
105#[cfg_attr(feature = "defmt", derive(defmt::Format))]
106#[derive(Clone, Copy, Debug, PartialEq, Eq)]
107pub enum INITSR {
108    ///0: Calendar has not been initialized
109    NotInitalized = 0,
110    ///1: Calendar has been initialized
111    Initalized = 1,
112}
113impl From<INITSR> for bool {
114    #[inline(always)]
115    fn from(variant: INITSR) -> Self {
116        variant as u8 != 0
117    }
118}
119///Field `INITS` reader - Initialization status flag
120pub type INITS_R = crate::BitReader<INITSR>;
121impl INITS_R {
122    ///Get enumerated values variant
123    #[inline(always)]
124    pub const fn variant(&self) -> INITSR {
125        match self.bits {
126            false => INITSR::NotInitalized,
127            true => INITSR::Initalized,
128        }
129    }
130    ///Calendar has not been initialized
131    #[inline(always)]
132    pub fn is_not_initalized(&self) -> bool {
133        *self == INITSR::NotInitalized
134    }
135    ///Calendar has been initialized
136    #[inline(always)]
137    pub fn is_initalized(&self) -> bool {
138        *self == INITSR::Initalized
139    }
140}
141/**Registers synchronization flag
142
143Value on reset: 0*/
144#[cfg_attr(feature = "defmt", derive(defmt::Format))]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146pub enum RSFR {
147    ///0: Calendar shadow registers not yet synchronized
148    NotSynced = 0,
149    ///1: Calendar shadow registers synchronized
150    Synced = 1,
151}
152impl From<RSFR> for bool {
153    #[inline(always)]
154    fn from(variant: RSFR) -> Self {
155        variant as u8 != 0
156    }
157}
158///Field `RSF` reader - Registers synchronization flag
159pub type RSF_R = crate::BitReader<RSFR>;
160impl RSF_R {
161    ///Get enumerated values variant
162    #[inline(always)]
163    pub const fn variant(&self) -> RSFR {
164        match self.bits {
165            false => RSFR::NotSynced,
166            true => RSFR::Synced,
167        }
168    }
169    ///Calendar shadow registers not yet synchronized
170    #[inline(always)]
171    pub fn is_not_synced(&self) -> bool {
172        *self == RSFR::NotSynced
173    }
174    ///Calendar shadow registers synchronized
175    #[inline(always)]
176    pub fn is_synced(&self) -> bool {
177        *self == RSFR::Synced
178    }
179}
180/**Registers synchronization flag
181
182Value on reset: 0*/
183#[cfg_attr(feature = "defmt", derive(defmt::Format))]
184#[derive(Clone, Copy, Debug, PartialEq, Eq)]
185pub enum RSFW {
186    ///0: This flag is cleared by software by writing 0
187    Clear = 0,
188}
189impl From<RSFW> for bool {
190    #[inline(always)]
191    fn from(variant: RSFW) -> Self {
192        variant as u8 != 0
193    }
194}
195///Field `RSF` writer - Registers synchronization flag
196pub type RSF_W<'a, REG> = crate::BitWriter0C<'a, REG, RSFW>;
197impl<'a, REG> RSF_W<'a, REG>
198where
199    REG: crate::Writable + crate::RegisterSpec,
200{
201    ///This flag is cleared by software by writing 0
202    #[inline(always)]
203    pub fn clear(self) -> &'a mut crate::W<REG> {
204        self.variant(RSFW::Clear)
205    }
206}
207/**Initialization flag
208
209Value on reset: 0*/
210#[cfg_attr(feature = "defmt", derive(defmt::Format))]
211#[derive(Clone, Copy, Debug, PartialEq, Eq)]
212pub enum INITFR {
213    ///0: Calendar registers update is not allowed
214    NotAllowed = 0,
215    ///1: Calendar registers update is allowed
216    Allowed = 1,
217}
218impl From<INITFR> for bool {
219    #[inline(always)]
220    fn from(variant: INITFR) -> Self {
221        variant as u8 != 0
222    }
223}
224///Field `INITF` reader - Initialization flag
225pub type INITF_R = crate::BitReader<INITFR>;
226impl INITF_R {
227    ///Get enumerated values variant
228    #[inline(always)]
229    pub const fn variant(&self) -> INITFR {
230        match self.bits {
231            false => INITFR::NotAllowed,
232            true => INITFR::Allowed,
233        }
234    }
235    ///Calendar registers update is not allowed
236    #[inline(always)]
237    pub fn is_not_allowed(&self) -> bool {
238        *self == INITFR::NotAllowed
239    }
240    ///Calendar registers update is allowed
241    #[inline(always)]
242    pub fn is_allowed(&self) -> bool {
243        *self == INITFR::Allowed
244    }
245}
246/**Initialization mode
247
248Value on reset: 0*/
249#[cfg_attr(feature = "defmt", derive(defmt::Format))]
250#[derive(Clone, Copy, Debug, PartialEq, Eq)]
251pub enum INIT {
252    ///0: Free running mode
253    FreeRunningMode = 0,
254    ///1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
255    InitMode = 1,
256}
257impl From<INIT> for bool {
258    #[inline(always)]
259    fn from(variant: INIT) -> Self {
260        variant as u8 != 0
261    }
262}
263///Field `INIT` reader - Initialization mode
264pub type INIT_R = crate::BitReader<INIT>;
265impl INIT_R {
266    ///Get enumerated values variant
267    #[inline(always)]
268    pub const fn variant(&self) -> INIT {
269        match self.bits {
270            false => INIT::FreeRunningMode,
271            true => INIT::InitMode,
272        }
273    }
274    ///Free running mode
275    #[inline(always)]
276    pub fn is_free_running_mode(&self) -> bool {
277        *self == INIT::FreeRunningMode
278    }
279    ///Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
280    #[inline(always)]
281    pub fn is_init_mode(&self) -> bool {
282        *self == INIT::InitMode
283    }
284}
285///Field `INIT` writer - Initialization mode
286pub type INIT_W<'a, REG> = crate::BitWriter<'a, REG, INIT>;
287impl<'a, REG> INIT_W<'a, REG>
288where
289    REG: crate::Writable + crate::RegisterSpec,
290{
291    ///Free running mode
292    #[inline(always)]
293    pub fn free_running_mode(self) -> &'a mut crate::W<REG> {
294        self.variant(INIT::FreeRunningMode)
295    }
296    ///Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
297    #[inline(always)]
298    pub fn init_mode(self) -> &'a mut crate::W<REG> {
299        self.variant(INIT::InitMode)
300    }
301}
302/**Recalibration pending Flag
303
304Value on reset: 0*/
305#[cfg_attr(feature = "defmt", derive(defmt::Format))]
306#[derive(Clone, Copy, Debug, PartialEq, Eq)]
307pub enum RECALPFR {
308    ///1: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
309    Pending = 1,
310}
311impl From<RECALPFR> for bool {
312    #[inline(always)]
313    fn from(variant: RECALPFR) -> Self {
314        variant as u8 != 0
315    }
316}
317///Field `RECALPF` reader - Recalibration pending Flag
318pub type RECALPF_R = crate::BitReader<RECALPFR>;
319impl RECALPF_R {
320    ///Get enumerated values variant
321    #[inline(always)]
322    pub const fn variant(&self) -> Option<RECALPFR> {
323        match self.bits {
324            true => Some(RECALPFR::Pending),
325            _ => None,
326        }
327    }
328    ///The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
329    #[inline(always)]
330    pub fn is_pending(&self) -> bool {
331        *self == RECALPFR::Pending
332    }
333}
334impl R {
335    ///Alarm (A,B) write flag
336    ///
337    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAWF` field.</div>
338    #[inline(always)]
339    pub fn alrwf(&self, n: u8) -> ALRWF_R {
340        #[allow(clippy::no_effect)]
341        [(); 2][n as usize];
342        ALRWF_R::new(((self.bits >> n) & 1) != 0)
343    }
344    ///Iterator for array of:
345    ///Alarm (A,B) write flag
346    #[inline(always)]
347    pub fn alrwf_iter(&self) -> impl Iterator<Item = ALRWF_R> + '_ {
348        (0..2).map(move |n| ALRWF_R::new(((self.bits >> n) & 1) != 0))
349    }
350    ///Bit 0 - Alarm A write flag
351    #[inline(always)]
352    pub fn alrawf(&self) -> ALRWF_R {
353        ALRWF_R::new((self.bits & 1) != 0)
354    }
355    ///Bit 1 - Alarm B write flag
356    #[inline(always)]
357    pub fn alrbwf(&self) -> ALRWF_R {
358        ALRWF_R::new(((self.bits >> 1) & 1) != 0)
359    }
360    ///Bit 2 - Wakeup timer write flag
361    #[inline(always)]
362    pub fn wutwf(&self) -> WUTWF_R {
363        WUTWF_R::new(((self.bits >> 2) & 1) != 0)
364    }
365    ///Bit 3 - Shift operation pending
366    #[inline(always)]
367    pub fn shpf(&self) -> SHPF_R {
368        SHPF_R::new(((self.bits >> 3) & 1) != 0)
369    }
370    ///Bit 4 - Initialization status flag
371    #[inline(always)]
372    pub fn inits(&self) -> INITS_R {
373        INITS_R::new(((self.bits >> 4) & 1) != 0)
374    }
375    ///Bit 5 - Registers synchronization flag
376    #[inline(always)]
377    pub fn rsf(&self) -> RSF_R {
378        RSF_R::new(((self.bits >> 5) & 1) != 0)
379    }
380    ///Bit 6 - Initialization flag
381    #[inline(always)]
382    pub fn initf(&self) -> INITF_R {
383        INITF_R::new(((self.bits >> 6) & 1) != 0)
384    }
385    ///Bit 7 - Initialization mode
386    #[inline(always)]
387    pub fn init(&self) -> INIT_R {
388        INIT_R::new(((self.bits >> 7) & 1) != 0)
389    }
390    ///Bit 16 - Recalibration pending Flag
391    #[inline(always)]
392    pub fn recalpf(&self) -> RECALPF_R {
393        RECALPF_R::new(((self.bits >> 16) & 1) != 0)
394    }
395}
396impl core::fmt::Debug for R {
397    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
398        f.debug_struct("ICSR")
399            .field("alrawf", &self.alrawf())
400            .field("alrbwf", &self.alrbwf())
401            .field("wutwf", &self.wutwf())
402            .field("shpf", &self.shpf())
403            .field("inits", &self.inits())
404            .field("rsf", &self.rsf())
405            .field("initf", &self.initf())
406            .field("init", &self.init())
407            .field("recalpf", &self.recalpf())
408            .finish()
409    }
410}
411impl W {
412    ///Bit 3 - Shift operation pending
413    #[inline(always)]
414    pub fn shpf(&mut self) -> SHPF_W<ICSRrs> {
415        SHPF_W::new(self, 3)
416    }
417    ///Bit 5 - Registers synchronization flag
418    #[inline(always)]
419    pub fn rsf(&mut self) -> RSF_W<ICSRrs> {
420        RSF_W::new(self, 5)
421    }
422    ///Bit 7 - Initialization mode
423    #[inline(always)]
424    pub fn init(&mut self) -> INIT_W<ICSRrs> {
425        INIT_W::new(self, 7)
426    }
427}
428/**initialization and status register
429
430You can [`read`](crate::Reg::read) this register and get [`icsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
431
432See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#RTC:ICSR)*/
433pub struct ICSRrs;
434impl crate::RegisterSpec for ICSRrs {
435    type Ux = u32;
436}
437///`read()` method returns [`icsr::R`](R) reader structure
438impl crate::Readable for ICSRrs {}
439///`write(|w| ..)` method takes [`icsr::W`](W) writer structure
440impl crate::Writable for ICSRrs {
441    type Safety = crate::Unsafe;
442    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x20;
443}
444///`reset()` method sets ICSR to value 0x07
445impl crate::Resettable for ICSRrs {
446    const RESET_VALUE: u32 = 0x07;
447}
stm32g0/stm32g041/rtc/icsr.rs

stm32g0/stm32g041/rtc/
icsr.rs
