stm32g0/stm32g030/tim3/
tisel.rs1pub type R = crate::R<TISELrs>;
3pub type W = crate::W<TISELrs>;
5pub type TI1SEL_R = crate::FieldReader;
7pub type TI1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9pub type TI2SEL_R = crate::FieldReader;
11pub type TI2SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14 #[inline(always)]
16 pub fn ti1sel(&self) -> TI1SEL_R {
17 TI1SEL_R::new((self.bits & 0x0f) as u8)
18 }
19 #[inline(always)]
21 pub fn ti2sel(&self) -> TI2SEL_R {
22 TI2SEL_R::new(((self.bits >> 8) & 0x0f) as u8)
23 }
24}
25impl core::fmt::Debug for R {
26 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27 f.debug_struct("TISEL")
28 .field("ti1sel", &self.ti1sel())
29 .field("ti2sel", &self.ti2sel())
30 .finish()
31 }
32}
33impl W {
34 #[inline(always)]
36 pub fn ti1sel(&mut self) -> TI1SEL_W<TISELrs> {
37 TI1SEL_W::new(self, 0)
38 }
39 #[inline(always)]
41 pub fn ti2sel(&mut self) -> TI2SEL_W<TISELrs> {
42 TI2SEL_W::new(self, 8)
43 }
44}
45pub struct TISELrs;
51impl crate::RegisterSpec for TISELrs {
52 type Ux = u32;
53}
54impl crate::Readable for TISELrs {}
56impl crate::Writable for TISELrs {
58 type Safety = crate::Unsafe;
59}
60impl crate::Resettable for TISELrs {}