stm32g0/stm32g030/tim3/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**Capture/compare DMA selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CCDS {
11    ///0: CCx DMA request sent when CCx event occurs
12    OnCompare = 0,
13    ///1: CCx DMA request sent when update event occurs
14    OnUpdate = 1,
15}
16impl From<CCDS> for bool {
17    #[inline(always)]
18    fn from(variant: CCDS) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCDS` reader - Capture/compare DMA selection
23pub type CCDS_R = crate::BitReader<CCDS>;
24impl CCDS_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CCDS {
28        match self.bits {
29            false => CCDS::OnCompare,
30            true => CCDS::OnUpdate,
31        }
32    }
33    ///CCx DMA request sent when CCx event occurs
34    #[inline(always)]
35    pub fn is_on_compare(&self) -> bool {
36        *self == CCDS::OnCompare
37    }
38    ///CCx DMA request sent when update event occurs
39    #[inline(always)]
40    pub fn is_on_update(&self) -> bool {
41        *self == CCDS::OnUpdate
42    }
43}
44///Field `CCDS` writer - Capture/compare DMA selection
45pub type CCDS_W<'a, REG> = crate::BitWriter<'a, REG, CCDS>;
46impl<'a, REG> CCDS_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///CCx DMA request sent when CCx event occurs
51    #[inline(always)]
52    pub fn on_compare(self) -> &'a mut crate::W<REG> {
53        self.variant(CCDS::OnCompare)
54    }
55    ///CCx DMA request sent when update event occurs
56    #[inline(always)]
57    pub fn on_update(self) -> &'a mut crate::W<REG> {
58        self.variant(CCDS::OnUpdate)
59    }
60}
61///Field `MMS` reader - Master mode selection
62pub type MMS_R = crate::FieldReader;
63///Field `MMS` writer - Master mode selection
64pub type MMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
65/**TI1 selection
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum TI1S {
71    ///0: The TIMx_CH1 pin is connected to TI1 input
72    Normal = 0,
73    ///1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
74    Xor = 1,
75}
76impl From<TI1S> for bool {
77    #[inline(always)]
78    fn from(variant: TI1S) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `TI1S` reader - TI1 selection
83pub type TI1S_R = crate::BitReader<TI1S>;
84impl TI1S_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> TI1S {
88        match self.bits {
89            false => TI1S::Normal,
90            true => TI1S::Xor,
91        }
92    }
93    ///The TIMx_CH1 pin is connected to TI1 input
94    #[inline(always)]
95    pub fn is_normal(&self) -> bool {
96        *self == TI1S::Normal
97    }
98    ///The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
99    #[inline(always)]
100    pub fn is_xor(&self) -> bool {
101        *self == TI1S::Xor
102    }
103}
104///Field `TI1S` writer - TI1 selection
105pub type TI1S_W<'a, REG> = crate::BitWriter<'a, REG, TI1S>;
106impl<'a, REG> TI1S_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///The TIMx_CH1 pin is connected to TI1 input
111    #[inline(always)]
112    pub fn normal(self) -> &'a mut crate::W<REG> {
113        self.variant(TI1S::Normal)
114    }
115    ///The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
116    #[inline(always)]
117    pub fn xor(self) -> &'a mut crate::W<REG> {
118        self.variant(TI1S::Xor)
119    }
120}
121impl R {
122    ///Bit 3 - Capture/compare DMA selection
123    #[inline(always)]
124    pub fn ccds(&self) -> CCDS_R {
125        CCDS_R::new(((self.bits >> 3) & 1) != 0)
126    }
127    ///Bits 4:6 - Master mode selection
128    #[inline(always)]
129    pub fn mms(&self) -> MMS_R {
130        MMS_R::new(((self.bits >> 4) & 7) as u8)
131    }
132    ///Bit 7 - TI1 selection
133    #[inline(always)]
134    pub fn ti1s(&self) -> TI1S_R {
135        TI1S_R::new(((self.bits >> 7) & 1) != 0)
136    }
137}
138impl core::fmt::Debug for R {
139    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
140        f.debug_struct("CR2")
141            .field("ti1s", &self.ti1s())
142            .field("mms", &self.mms())
143            .field("ccds", &self.ccds())
144            .finish()
145    }
146}
147impl W {
148    ///Bit 3 - Capture/compare DMA selection
149    #[inline(always)]
150    pub fn ccds(&mut self) -> CCDS_W<CR2rs> {
151        CCDS_W::new(self, 3)
152    }
153    ///Bits 4:6 - Master mode selection
154    #[inline(always)]
155    pub fn mms(&mut self) -> MMS_W<CR2rs> {
156        MMS_W::new(self, 4)
157    }
158    ///Bit 7 - TI1 selection
159    #[inline(always)]
160    pub fn ti1s(&mut self) -> TI1S_W<CR2rs> {
161        TI1S_W::new(self, 7)
162    }
163}
164/**control register 2
165
166You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#TIM3:CR2)*/
169pub struct CR2rs;
170impl crate::RegisterSpec for CR2rs {
171    type Ux = u32;
172}
173///`read()` method returns [`cr2::R`](R) reader structure
174impl crate::Readable for CR2rs {}
175///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
176impl crate::Writable for CR2rs {
177    type Safety = crate::Unsafe;
178}
179///`reset()` method sets CR2 to value 0
180impl crate::Resettable for CR2rs {}
stm32g0/stm32g030/tim3/cr2.rs

stm32g0/stm32g030/tim3/
cr2.rs
