stm32g0/stm32g030/tim14/
tisel.rs

1///Register `TISEL` reader
2pub type R = crate::R<TISELrs>;
3///Register `TISEL` writer
4pub type W = crate::W<TISELrs>;
5///Field `TISEL` reader - TI1\[0\] to TI1\[15\] input selection
6pub type TISEL_R = crate::FieldReader;
7///Field `TISEL` writer - TI1\[0\] to TI1\[15\] input selection
8pub type TISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9impl R {
10    ///Bits 0:3 - TI1\[0\] to TI1\[15\] input selection
11    #[inline(always)]
12    pub fn tisel(&self) -> TISEL_R {
13        TISEL_R::new((self.bits & 0x0f) as u8)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("TISEL")
19            .field("tisel", &self.tisel())
20            .finish()
21    }
22}
23impl W {
24    ///Bits 0:3 - TI1\[0\] to TI1\[15\] input selection
25    #[inline(always)]
26    pub fn tisel(&mut self) -> TISEL_W<TISELrs> {
27        TISEL_W::new(self, 0)
28    }
29}
30/**TIM timer input selection register
31
32You can [`read`](crate::Reg::read) this register and get [`tisel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
33
34See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#TIM14:TISEL)*/
35pub struct TISELrs;
36impl crate::RegisterSpec for TISELrs {
37    type Ux = u32;
38}
39///`read()` method returns [`tisel::R`](R) reader structure
40impl crate::Readable for TISELrs {}
41///`write(|w| ..)` method takes [`tisel::W`](W) writer structure
42impl crate::Writable for TISELrs {
43    type Safety = crate::Unsafe;
44}
45///`reset()` method sets TISEL to value 0
46impl crate::Resettable for TISELrs {}
stm32g0/stm32g030/tim14/tisel.rs

stm32g0/stm32g030/tim14/
tisel.rs
