stm32g0/stm32g030/tim1/
or1.rs

1///Register `OR1` reader
2pub type R = crate::R<OR1rs>;
3///Register `OR1` writer
4pub type W = crate::W<OR1rs>;
5///Field `OCREF_CLR` reader - Ocref_clr source selection
6pub type OCREF_CLR_R = crate::BitReader;
7///Field `OCREF_CLR` writer - Ocref_clr source selection
8pub type OCREF_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    ///Bit 0 - Ocref_clr source selection
11    #[inline(always)]
12    pub fn ocref_clr(&self) -> OCREF_CLR_R {
13        OCREF_CLR_R::new((self.bits & 1) != 0)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("OR1")
19            .field("ocref_clr", &self.ocref_clr())
20            .finish()
21    }
22}
23impl W {
24    ///Bit 0 - Ocref_clr source selection
25    #[inline(always)]
26    pub fn ocref_clr(&mut self) -> OCREF_CLR_W<OR1rs> {
27        OCREF_CLR_W::new(self, 0)
28    }
29}
30/**option register 1
31
32You can [`read`](crate::Reg::read) this register and get [`or1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
33
34See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#TIM1:OR1)*/
35pub struct OR1rs;
36impl crate::RegisterSpec for OR1rs {
37    type Ux = u32;
38}
39///`read()` method returns [`or1::R`](R) reader structure
40impl crate::Readable for OR1rs {}
41///`write(|w| ..)` method takes [`or1::W`](W) writer structure
42impl crate::Writable for OR1rs {
43    type Safety = crate::Unsafe;
44}
45///`reset()` method sets OR1 to value 0
46impl crate::Resettable for OR1rs {}
stm32g0/stm32g030/tim1/or1.rs

stm32g0/stm32g030/tim1/
or1.rs
