stm32g0/stm32g030/adc/cr.rs
1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ADENR {
11 ///0: ADC disabled
12 Disabled = 0,
13 ///1: ADC enabled
14 Enabled = 1,
15}
16impl From<ADENR> for bool {
17 #[inline(always)]
18 fn from(variant: ADENR) -> Self {
19 variant as u8 != 0
20 }
21}
22///Field `ADEN` reader - ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
23pub type ADEN_R = crate::BitReader<ADENR>;
24impl ADEN_R {
25 ///Get enumerated values variant
26 #[inline(always)]
27 pub const fn variant(&self) -> ADENR {
28 match self.bits {
29 false => ADENR::Disabled,
30 true => ADENR::Enabled,
31 }
32 }
33 ///ADC disabled
34 #[inline(always)]
35 pub fn is_disabled(&self) -> bool {
36 *self == ADENR::Disabled
37 }
38 ///ADC enabled
39 #[inline(always)]
40 pub fn is_enabled(&self) -> bool {
41 *self == ADENR::Enabled
42 }
43}
44/**ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum ADENW {
50 ///1: Enable the ADC
51 Enabled = 1,
52}
53impl From<ADENW> for bool {
54 #[inline(always)]
55 fn from(variant: ADENW) -> Self {
56 variant as u8 != 0
57 }
58}
59///Field `ADEN` writer - ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
60pub type ADEN_W<'a, REG> = crate::BitWriter1S<'a, REG, ADENW>;
61impl<'a, REG> ADEN_W<'a, REG>
62where
63 REG: crate::Writable + crate::RegisterSpec,
64{
65 ///Enable the ADC
66 #[inline(always)]
67 pub fn enabled(self) -> &'a mut crate::W<REG> {
68 self.variant(ADENW::Enabled)
69 }
70}
71/**ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
72
73Value on reset: 0*/
74#[cfg_attr(feature = "defmt", derive(defmt::Format))]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum ADDISR {
77 ///0: No disable command active
78 NotDisabling = 0,
79 ///1: ADC disabling
80 Disabling = 1,
81}
82impl From<ADDISR> for bool {
83 #[inline(always)]
84 fn from(variant: ADDISR) -> Self {
85 variant as u8 != 0
86 }
87}
88///Field `ADDIS` reader - ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
89pub type ADDIS_R = crate::BitReader<ADDISR>;
90impl ADDIS_R {
91 ///Get enumerated values variant
92 #[inline(always)]
93 pub const fn variant(&self) -> ADDISR {
94 match self.bits {
95 false => ADDISR::NotDisabling,
96 true => ADDISR::Disabling,
97 }
98 }
99 ///No disable command active
100 #[inline(always)]
101 pub fn is_not_disabling(&self) -> bool {
102 *self == ADDISR::NotDisabling
103 }
104 ///ADC disabling
105 #[inline(always)]
106 pub fn is_disabling(&self) -> bool {
107 *self == ADDISR::Disabling
108 }
109}
110/**ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum ADDISW {
116 ///1: Disable the ADC
117 Disable = 1,
118}
119impl From<ADDISW> for bool {
120 #[inline(always)]
121 fn from(variant: ADDISW) -> Self {
122 variant as u8 != 0
123 }
124}
125///Field `ADDIS` writer - ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
126pub type ADDIS_W<'a, REG> = crate::BitWriter1S<'a, REG, ADDISW>;
127impl<'a, REG> ADDIS_W<'a, REG>
128where
129 REG: crate::Writable + crate::RegisterSpec,
130{
131 ///Disable the ADC
132 #[inline(always)]
133 pub fn disable(self) -> &'a mut crate::W<REG> {
134 self.variant(ADDISW::Disable)
135 }
136}
137/**ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
138
139Value on reset: 0*/
140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
142pub enum ADSTARTR {
143 ///0: No conversion ongoing
144 NotActive = 0,
145 ///1: ADC operating and may be converting
146 Active = 1,
147}
148impl From<ADSTARTR> for bool {
149 #[inline(always)]
150 fn from(variant: ADSTARTR) -> Self {
151 variant as u8 != 0
152 }
153}
154///Field `ADSTART` reader - ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
155pub type ADSTART_R = crate::BitReader<ADSTARTR>;
156impl ADSTART_R {
157 ///Get enumerated values variant
158 #[inline(always)]
159 pub const fn variant(&self) -> ADSTARTR {
160 match self.bits {
161 false => ADSTARTR::NotActive,
162 true => ADSTARTR::Active,
163 }
164 }
165 ///No conversion ongoing
166 #[inline(always)]
167 pub fn is_not_active(&self) -> bool {
168 *self == ADSTARTR::NotActive
169 }
170 ///ADC operating and may be converting
171 #[inline(always)]
172 pub fn is_active(&self) -> bool {
173 *self == ADSTARTR::Active
174 }
175}
176/**ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum ADSTARTW {
182 ///1: Start the ADC conversion (may be delayed for hardware triggers)
183 StartConversion = 1,
184}
185impl From<ADSTARTW> for bool {
186 #[inline(always)]
187 fn from(variant: ADSTARTW) -> Self {
188 variant as u8 != 0
189 }
190}
191///Field `ADSTART` writer - ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
192pub type ADSTART_W<'a, REG> = crate::BitWriter1S<'a, REG, ADSTARTW>;
193impl<'a, REG> ADSTART_W<'a, REG>
194where
195 REG: crate::Writable + crate::RegisterSpec,
196{
197 ///Start the ADC conversion (may be delayed for hardware triggers)
198 #[inline(always)]
199 pub fn start_conversion(self) -> &'a mut crate::W<REG> {
200 self.variant(ADSTARTW::StartConversion)
201 }
202}
203/**ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
204
205Value on reset: 0*/
206#[cfg_attr(feature = "defmt", derive(defmt::Format))]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum ADSTPR {
209 ///0: No stop command active
210 NotStopping = 0,
211 ///1: ADC stopping conversion
212 Stopping = 1,
213}
214impl From<ADSTPR> for bool {
215 #[inline(always)]
216 fn from(variant: ADSTPR) -> Self {
217 variant as u8 != 0
218 }
219}
220///Field `ADSTP` reader - ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
221pub type ADSTP_R = crate::BitReader<ADSTPR>;
222impl ADSTP_R {
223 ///Get enumerated values variant
224 #[inline(always)]
225 pub const fn variant(&self) -> ADSTPR {
226 match self.bits {
227 false => ADSTPR::NotStopping,
228 true => ADSTPR::Stopping,
229 }
230 }
231 ///No stop command active
232 #[inline(always)]
233 pub fn is_not_stopping(&self) -> bool {
234 *self == ADSTPR::NotStopping
235 }
236 ///ADC stopping conversion
237 #[inline(always)]
238 pub fn is_stopping(&self) -> bool {
239 *self == ADSTPR::Stopping
240 }
241}
242/**ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
243
244Value on reset: 0*/
245#[cfg_attr(feature = "defmt", derive(defmt::Format))]
246#[derive(Clone, Copy, Debug, PartialEq, Eq)]
247pub enum ADSTPW {
248 ///1: Stop the active conversion
249 StopConversion = 1,
250}
251impl From<ADSTPW> for bool {
252 #[inline(always)]
253 fn from(variant: ADSTPW) -> Self {
254 variant as u8 != 0
255 }
256}
257///Field `ADSTP` writer - ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
258pub type ADSTP_W<'a, REG> = crate::BitWriter1S<'a, REG, ADSTPW>;
259impl<'a, REG> ADSTP_W<'a, REG>
260where
261 REG: crate::Writable + crate::RegisterSpec,
262{
263 ///Stop the active conversion
264 #[inline(always)]
265 pub fn stop_conversion(self) -> &'a mut crate::W<REG> {
266 self.variant(ADSTPW::StopConversion)
267 }
268}
269/**ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
270
271Value on reset: 0*/
272#[cfg_attr(feature = "defmt", derive(defmt::Format))]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum ADVREGEN {
275 ///0: ADC voltage regulator disabled
276 Disabled = 0,
277 ///1: ADC voltage regulator enabled
278 Enabled = 1,
279}
280impl From<ADVREGEN> for bool {
281 #[inline(always)]
282 fn from(variant: ADVREGEN) -> Self {
283 variant as u8 != 0
284 }
285}
286///Field `ADVREGEN` reader - ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
287pub type ADVREGEN_R = crate::BitReader<ADVREGEN>;
288impl ADVREGEN_R {
289 ///Get enumerated values variant
290 #[inline(always)]
291 pub const fn variant(&self) -> ADVREGEN {
292 match self.bits {
293 false => ADVREGEN::Disabled,
294 true => ADVREGEN::Enabled,
295 }
296 }
297 ///ADC voltage regulator disabled
298 #[inline(always)]
299 pub fn is_disabled(&self) -> bool {
300 *self == ADVREGEN::Disabled
301 }
302 ///ADC voltage regulator enabled
303 #[inline(always)]
304 pub fn is_enabled(&self) -> bool {
305 *self == ADVREGEN::Enabled
306 }
307}
308///Field `ADVREGEN` writer - ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
309pub type ADVREGEN_W<'a, REG> = crate::BitWriter<'a, REG, ADVREGEN>;
310impl<'a, REG> ADVREGEN_W<'a, REG>
311where
312 REG: crate::Writable + crate::RegisterSpec,
313{
314 ///ADC voltage regulator disabled
315 #[inline(always)]
316 pub fn disabled(self) -> &'a mut crate::W<REG> {
317 self.variant(ADVREGEN::Disabled)
318 }
319 ///ADC voltage regulator enabled
320 #[inline(always)]
321 pub fn enabled(self) -> &'a mut crate::W<REG> {
322 self.variant(ADVREGEN::Enabled)
323 }
324}
325/**ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
326
327Value on reset: 0*/
328#[cfg_attr(feature = "defmt", derive(defmt::Format))]
329#[derive(Clone, Copy, Debug, PartialEq, Eq)]
330pub enum ADCALR {
331 ///0: ADC calibration either not yet performed or completed
332 NotCalibrating = 0,
333 ///1: ADC calibration in progress
334 Calibrating = 1,
335}
336impl From<ADCALR> for bool {
337 #[inline(always)]
338 fn from(variant: ADCALR) -> Self {
339 variant as u8 != 0
340 }
341}
342///Field `ADCAL` reader - ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
343pub type ADCAL_R = crate::BitReader<ADCALR>;
344impl ADCAL_R {
345 ///Get enumerated values variant
346 #[inline(always)]
347 pub const fn variant(&self) -> ADCALR {
348 match self.bits {
349 false => ADCALR::NotCalibrating,
350 true => ADCALR::Calibrating,
351 }
352 }
353 ///ADC calibration either not yet performed or completed
354 #[inline(always)]
355 pub fn is_not_calibrating(&self) -> bool {
356 *self == ADCALR::NotCalibrating
357 }
358 ///ADC calibration in progress
359 #[inline(always)]
360 pub fn is_calibrating(&self) -> bool {
361 *self == ADCALR::Calibrating
362 }
363}
364/**ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
365
366Value on reset: 0*/
367#[cfg_attr(feature = "defmt", derive(defmt::Format))]
368#[derive(Clone, Copy, Debug, PartialEq, Eq)]
369pub enum ADCALW {
370 ///1: Start the ADC calibration sequence
371 StartCalibration = 1,
372}
373impl From<ADCALW> for bool {
374 #[inline(always)]
375 fn from(variant: ADCALW) -> Self {
376 variant as u8 != 0
377 }
378}
379///Field `ADCAL` writer - ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
380pub type ADCAL_W<'a, REG> = crate::BitWriter1S<'a, REG, ADCALW>;
381impl<'a, REG> ADCAL_W<'a, REG>
382where
383 REG: crate::Writable + crate::RegisterSpec,
384{
385 ///Start the ADC calibration sequence
386 #[inline(always)]
387 pub fn start_calibration(self) -> &'a mut crate::W<REG> {
388 self.variant(ADCALW::StartCalibration)
389 }
390}
391impl R {
392 ///Bit 0 - ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
393 #[inline(always)]
394 pub fn aden(&self) -> ADEN_R {
395 ADEN_R::new((self.bits & 1) != 0)
396 }
397 ///Bit 1 - ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
398 #[inline(always)]
399 pub fn addis(&self) -> ADDIS_R {
400 ADDIS_R::new(((self.bits >> 1) & 1) != 0)
401 }
402 ///Bit 2 - ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
403 #[inline(always)]
404 pub fn adstart(&self) -> ADSTART_R {
405 ADSTART_R::new(((self.bits >> 2) & 1) != 0)
406 }
407 ///Bit 4 - ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
408 #[inline(always)]
409 pub fn adstp(&self) -> ADSTP_R {
410 ADSTP_R::new(((self.bits >> 4) & 1) != 0)
411 }
412 ///Bit 28 - ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
413 #[inline(always)]
414 pub fn advregen(&self) -> ADVREGEN_R {
415 ADVREGEN_R::new(((self.bits >> 28) & 1) != 0)
416 }
417 ///Bit 31 - ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
418 #[inline(always)]
419 pub fn adcal(&self) -> ADCAL_R {
420 ADCAL_R::new(((self.bits >> 31) & 1) != 0)
421 }
422}
423impl core::fmt::Debug for R {
424 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
425 f.debug_struct("CR")
426 .field("aden", &self.aden())
427 .field("addis", &self.addis())
428 .field("adstart", &self.adstart())
429 .field("adstp", &self.adstp())
430 .field("advregen", &self.advregen())
431 .field("adcal", &self.adcal())
432 .finish()
433 }
434}
435impl W {
436 ///Bit 0 - ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0)
437 #[inline(always)]
438 pub fn aden(&mut self) -> ADEN_W<CRrs> {
439 ADEN_W::new(self, 0)
440 }
441 ///Bit 1 - ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1' is only effective when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing)
442 #[inline(always)]
443 pub fn addis(&mut self) -> ADDIS_W<CRrs> {
444 ADDIS_W::new(self, 1)
445 }
446 ///Bit 2 - ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN \[1:0\] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored.
447 #[inline(always)]
448 pub fn adstart(&mut self) -> ADSTART_W<CRrs> {
449 ADSTART_W::new(self, 2)
450 }
451 ///Bit 4 - ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1' is only effective when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)
452 #[inline(always)]
453 pub fn adstp(&mut self) -> ADSTP_W<CRrs> {
454 ADSTP_W::new(self, 4)
455 }
456 ///Bit 28 - ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
457 #[inline(always)]
458 pub fn advregen(&mut self) -> ADVREGEN_W<CRrs> {
459 ADVREGEN_W::new(self, 28)
460 }
461 ///Bit 31 - ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing).
462 #[inline(always)]
463 pub fn adcal(&mut self) -> ADCAL_W<CRrs> {
464 ADCAL_W::new(self, 31)
465 }
466}
467/**ADC control register
468
469You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
470
471See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#ADC:CR)*/
472pub struct CRrs;
473impl crate::RegisterSpec for CRrs {
474 type Ux = u32;
475}
476///`read()` method returns [`cr::R`](R) reader structure
477impl crate::Readable for CRrs {}
478///`write(|w| ..)` method takes [`cr::W`](W) writer structure
479impl crate::Writable for CRrs {
480 type Safety = crate::Unsafe;
481 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0017;
482}
483///`reset()` method sets CR to value 0
484impl crate::Resettable for CRrs {}