stm32g0/stm32g030/adc/
chselr0.rs

1///Register `CHSELR0` reader
2pub type R = crate::R<CHSELR0rs>;
3///Register `CHSELR0` writer
4pub type W = crate::W<CHSELR0rs>;
5/**Channel-%s selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CHSEL0 {
11    ///0: Input Channel is not selected for conversion
12    NotSelected = 0,
13    ///1: Input Channel is selected for conversion
14    Selected = 1,
15}
16impl From<CHSEL0> for bool {
17    #[inline(always)]
18    fn from(variant: CHSEL0) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CHSEL(0-18)` reader - Channel-%s selection
23pub type CHSEL_R = crate::BitReader<CHSEL0>;
24impl CHSEL_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CHSEL0 {
28        match self.bits {
29            false => CHSEL0::NotSelected,
30            true => CHSEL0::Selected,
31        }
32    }
33    ///Input Channel is not selected for conversion
34    #[inline(always)]
35    pub fn is_not_selected(&self) -> bool {
36        *self == CHSEL0::NotSelected
37    }
38    ///Input Channel is selected for conversion
39    #[inline(always)]
40    pub fn is_selected(&self) -> bool {
41        *self == CHSEL0::Selected
42    }
43}
44///Field `CHSEL(0-18)` writer - Channel-%s selection
45pub type CHSEL_W<'a, REG> = crate::BitWriter<'a, REG, CHSEL0>;
46impl<'a, REG> CHSEL_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Input Channel is not selected for conversion
51    #[inline(always)]
52    pub fn not_selected(self) -> &'a mut crate::W<REG> {
53        self.variant(CHSEL0::NotSelected)
54    }
55    ///Input Channel is selected for conversion
56    #[inline(always)]
57    pub fn selected(self) -> &'a mut crate::W<REG> {
58        self.variant(CHSEL0::Selected)
59    }
60}
61impl R {
62    ///Channel-(0-18) selection
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CHSEL0` field.</div>
65    #[inline(always)]
66    pub fn chsel(&self, n: u8) -> CHSEL_R {
67        #[allow(clippy::no_effect)]
68        [(); 19][n as usize];
69        CHSEL_R::new(((self.bits >> n) & 1) != 0)
70    }
71    ///Iterator for array of:
72    ///Channel-(0-18) selection
73    #[inline(always)]
74    pub fn chsel_iter(&self) -> impl Iterator<Item = CHSEL_R> + '_ {
75        (0..19).map(move |n| CHSEL_R::new(((self.bits >> n) & 1) != 0))
76    }
77    ///Bit 0 - Channel-0 selection
78    #[inline(always)]
79    pub fn chsel0(&self) -> CHSEL_R {
80        CHSEL_R::new((self.bits & 1) != 0)
81    }
82    ///Bit 1 - Channel-1 selection
83    #[inline(always)]
84    pub fn chsel1(&self) -> CHSEL_R {
85        CHSEL_R::new(((self.bits >> 1) & 1) != 0)
86    }
87    ///Bit 2 - Channel-2 selection
88    #[inline(always)]
89    pub fn chsel2(&self) -> CHSEL_R {
90        CHSEL_R::new(((self.bits >> 2) & 1) != 0)
91    }
92    ///Bit 3 - Channel-3 selection
93    #[inline(always)]
94    pub fn chsel3(&self) -> CHSEL_R {
95        CHSEL_R::new(((self.bits >> 3) & 1) != 0)
96    }
97    ///Bit 4 - Channel-4 selection
98    #[inline(always)]
99    pub fn chsel4(&self) -> CHSEL_R {
100        CHSEL_R::new(((self.bits >> 4) & 1) != 0)
101    }
102    ///Bit 5 - Channel-5 selection
103    #[inline(always)]
104    pub fn chsel5(&self) -> CHSEL_R {
105        CHSEL_R::new(((self.bits >> 5) & 1) != 0)
106    }
107    ///Bit 6 - Channel-6 selection
108    #[inline(always)]
109    pub fn chsel6(&self) -> CHSEL_R {
110        CHSEL_R::new(((self.bits >> 6) & 1) != 0)
111    }
112    ///Bit 7 - Channel-7 selection
113    #[inline(always)]
114    pub fn chsel7(&self) -> CHSEL_R {
115        CHSEL_R::new(((self.bits >> 7) & 1) != 0)
116    }
117    ///Bit 8 - Channel-8 selection
118    #[inline(always)]
119    pub fn chsel8(&self) -> CHSEL_R {
120        CHSEL_R::new(((self.bits >> 8) & 1) != 0)
121    }
122    ///Bit 9 - Channel-9 selection
123    #[inline(always)]
124    pub fn chsel9(&self) -> CHSEL_R {
125        CHSEL_R::new(((self.bits >> 9) & 1) != 0)
126    }
127    ///Bit 10 - Channel-10 selection
128    #[inline(always)]
129    pub fn chsel10(&self) -> CHSEL_R {
130        CHSEL_R::new(((self.bits >> 10) & 1) != 0)
131    }
132    ///Bit 11 - Channel-11 selection
133    #[inline(always)]
134    pub fn chsel11(&self) -> CHSEL_R {
135        CHSEL_R::new(((self.bits >> 11) & 1) != 0)
136    }
137    ///Bit 12 - Channel-12 selection
138    #[inline(always)]
139    pub fn chsel12(&self) -> CHSEL_R {
140        CHSEL_R::new(((self.bits >> 12) & 1) != 0)
141    }
142    ///Bit 13 - Channel-13 selection
143    #[inline(always)]
144    pub fn chsel13(&self) -> CHSEL_R {
145        CHSEL_R::new(((self.bits >> 13) & 1) != 0)
146    }
147    ///Bit 14 - Channel-14 selection
148    #[inline(always)]
149    pub fn chsel14(&self) -> CHSEL_R {
150        CHSEL_R::new(((self.bits >> 14) & 1) != 0)
151    }
152    ///Bit 15 - Channel-15 selection
153    #[inline(always)]
154    pub fn chsel15(&self) -> CHSEL_R {
155        CHSEL_R::new(((self.bits >> 15) & 1) != 0)
156    }
157    ///Bit 16 - Channel-16 selection
158    #[inline(always)]
159    pub fn chsel16(&self) -> CHSEL_R {
160        CHSEL_R::new(((self.bits >> 16) & 1) != 0)
161    }
162    ///Bit 17 - Channel-17 selection
163    #[inline(always)]
164    pub fn chsel17(&self) -> CHSEL_R {
165        CHSEL_R::new(((self.bits >> 17) & 1) != 0)
166    }
167    ///Bit 18 - Channel-18 selection
168    #[inline(always)]
169    pub fn chsel18(&self) -> CHSEL_R {
170        CHSEL_R::new(((self.bits >> 18) & 1) != 0)
171    }
172}
173impl core::fmt::Debug for R {
174    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
175        f.debug_struct("CHSELR0")
176            .field("chsel0", &self.chsel0())
177            .field("chsel1", &self.chsel1())
178            .field("chsel2", &self.chsel2())
179            .field("chsel3", &self.chsel3())
180            .field("chsel4", &self.chsel4())
181            .field("chsel5", &self.chsel5())
182            .field("chsel6", &self.chsel6())
183            .field("chsel7", &self.chsel7())
184            .field("chsel8", &self.chsel8())
185            .field("chsel9", &self.chsel9())
186            .field("chsel10", &self.chsel10())
187            .field("chsel11", &self.chsel11())
188            .field("chsel12", &self.chsel12())
189            .field("chsel13", &self.chsel13())
190            .field("chsel14", &self.chsel14())
191            .field("chsel15", &self.chsel15())
192            .field("chsel16", &self.chsel16())
193            .field("chsel17", &self.chsel17())
194            .field("chsel18", &self.chsel18())
195            .finish()
196    }
197}
198impl W {
199    ///Channel-(0-18) selection
200    ///
201    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CHSEL0` field.</div>
202    #[inline(always)]
203    pub fn chsel(&mut self, n: u8) -> CHSEL_W<CHSELR0rs> {
204        #[allow(clippy::no_effect)]
205        [(); 19][n as usize];
206        CHSEL_W::new(self, n)
207    }
208    ///Bit 0 - Channel-0 selection
209    #[inline(always)]
210    pub fn chsel0(&mut self) -> CHSEL_W<CHSELR0rs> {
211        CHSEL_W::new(self, 0)
212    }
213    ///Bit 1 - Channel-1 selection
214    #[inline(always)]
215    pub fn chsel1(&mut self) -> CHSEL_W<CHSELR0rs> {
216        CHSEL_W::new(self, 1)
217    }
218    ///Bit 2 - Channel-2 selection
219    #[inline(always)]
220    pub fn chsel2(&mut self) -> CHSEL_W<CHSELR0rs> {
221        CHSEL_W::new(self, 2)
222    }
223    ///Bit 3 - Channel-3 selection
224    #[inline(always)]
225    pub fn chsel3(&mut self) -> CHSEL_W<CHSELR0rs> {
226        CHSEL_W::new(self, 3)
227    }
228    ///Bit 4 - Channel-4 selection
229    #[inline(always)]
230    pub fn chsel4(&mut self) -> CHSEL_W<CHSELR0rs> {
231        CHSEL_W::new(self, 4)
232    }
233    ///Bit 5 - Channel-5 selection
234    #[inline(always)]
235    pub fn chsel5(&mut self) -> CHSEL_W<CHSELR0rs> {
236        CHSEL_W::new(self, 5)
237    }
238    ///Bit 6 - Channel-6 selection
239    #[inline(always)]
240    pub fn chsel6(&mut self) -> CHSEL_W<CHSELR0rs> {
241        CHSEL_W::new(self, 6)
242    }
243    ///Bit 7 - Channel-7 selection
244    #[inline(always)]
245    pub fn chsel7(&mut self) -> CHSEL_W<CHSELR0rs> {
246        CHSEL_W::new(self, 7)
247    }
248    ///Bit 8 - Channel-8 selection
249    #[inline(always)]
250    pub fn chsel8(&mut self) -> CHSEL_W<CHSELR0rs> {
251        CHSEL_W::new(self, 8)
252    }
253    ///Bit 9 - Channel-9 selection
254    #[inline(always)]
255    pub fn chsel9(&mut self) -> CHSEL_W<CHSELR0rs> {
256        CHSEL_W::new(self, 9)
257    }
258    ///Bit 10 - Channel-10 selection
259    #[inline(always)]
260    pub fn chsel10(&mut self) -> CHSEL_W<CHSELR0rs> {
261        CHSEL_W::new(self, 10)
262    }
263    ///Bit 11 - Channel-11 selection
264    #[inline(always)]
265    pub fn chsel11(&mut self) -> CHSEL_W<CHSELR0rs> {
266        CHSEL_W::new(self, 11)
267    }
268    ///Bit 12 - Channel-12 selection
269    #[inline(always)]
270    pub fn chsel12(&mut self) -> CHSEL_W<CHSELR0rs> {
271        CHSEL_W::new(self, 12)
272    }
273    ///Bit 13 - Channel-13 selection
274    #[inline(always)]
275    pub fn chsel13(&mut self) -> CHSEL_W<CHSELR0rs> {
276        CHSEL_W::new(self, 13)
277    }
278    ///Bit 14 - Channel-14 selection
279    #[inline(always)]
280    pub fn chsel14(&mut self) -> CHSEL_W<CHSELR0rs> {
281        CHSEL_W::new(self, 14)
282    }
283    ///Bit 15 - Channel-15 selection
284    #[inline(always)]
285    pub fn chsel15(&mut self) -> CHSEL_W<CHSELR0rs> {
286        CHSEL_W::new(self, 15)
287    }
288    ///Bit 16 - Channel-16 selection
289    #[inline(always)]
290    pub fn chsel16(&mut self) -> CHSEL_W<CHSELR0rs> {
291        CHSEL_W::new(self, 16)
292    }
293    ///Bit 17 - Channel-17 selection
294    #[inline(always)]
295    pub fn chsel17(&mut self) -> CHSEL_W<CHSELR0rs> {
296        CHSEL_W::new(self, 17)
297    }
298    ///Bit 18 - Channel-18 selection
299    #[inline(always)]
300    pub fn chsel18(&mut self) -> CHSEL_W<CHSELR0rs> {
301        CHSEL_W::new(self, 18)
302    }
303}
304/**ADC channel selection register \[alternate\]
305
306You can [`read`](crate::Reg::read) this register and get [`chselr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chselr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
307
308See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#ADC:CHSELR0)*/
309pub struct CHSELR0rs;
310impl crate::RegisterSpec for CHSELR0rs {
311    type Ux = u32;
312}
313///`read()` method returns [`chselr0::R`](R) reader structure
314impl crate::Readable for CHSELR0rs {}
315///`write(|w| ..)` method takes [`chselr0::W`](W) writer structure
316impl crate::Writable for CHSELR0rs {
317    type Safety = crate::Unsafe;
318}
319///`reset()` method sets CHSELR0 to value 0
320impl crate::Resettable for CHSELR0rs {}
stm32g0/stm32g030/adc/chselr0.rs

stm32g0/stm32g030/adc/
chselr0.rs
