pub struct W(_);
Expand description
Register SMCR
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Implementations
sourceimpl W
impl W
sourcepub fn sms1(&mut self) -> SMS1_W<'_, 0>
pub fn sms1(&mut self) -> SMS1_W<'_, 0>
Bits 0:2 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
sourcepub fn occs(&mut self) -> OCCS_W<'_, 3>
pub fn occs(&mut self) -> OCCS_W<'_, 3>
Bit 3 - OCREF clear selection This bit is used to select the OCREF clear source
sourcepub fn ts1(&mut self) -> TS1_W<'_, 4>
pub fn ts1(&mut self) -> TS1_W<'_, 4>
Bits 4:6 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
sourcepub fn etf(&mut self) -> ETF_W<'_, 8>
pub fn etf(&mut self) -> ETF_W<'_, 8>
Bits 8:11 - External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
sourcepub fn etps(&mut self) -> ETPS_W<'_, 12>
pub fn etps(&mut self) -> ETPS_W<'_, 12>
Bits 12:13 - External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
sourcepub fn ece(&mut self) -> ECE_W<'_, 14>
pub fn ece(&mut self) -> ECE_W<'_, 14>
Bit 14 - External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
sourcepub fn etp(&mut self) -> ETP_W<'_, 15>
pub fn etp(&mut self) -> ETP_W<'_, 15>
Bit 15 - External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
sourcepub fn sms2(&mut self) -> SMS2_W<'_, 16>
pub fn sms2(&mut self) -> SMS2_W<'_, 16>
Bit 16 - Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, …) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
sourcepub fn ts2(&mut self) -> TS2_W<'_, 20>
pub fn ts2(&mut self) -> TS2_W<'_, 20>
Bits 20:21 - Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
Methods from Deref<Target = W<SMCR_SPEC>>
Trait Implementations
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more