stm32g0/stm32g0c1/tim1/
sr.rs

1#[doc = "Register `SR` reader"]
2pub struct R(crate::R<SR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SR` writer"]
17pub struct W(crate::W<SR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register.\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum UIF_A {
40    #[doc = "0: No update occurred"]
41    Clear = 0,
42    #[doc = "1: Update interrupt pending."]
43    UpdatePending = 1,
44}
45impl From<UIF_A> for bool {
46    #[inline(always)]
47    fn from(variant: UIF_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `UIF` reader - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register."]
52pub type UIF_R = crate::BitReader<UIF_A>;
53impl UIF_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> UIF_A {
57        match self.bits {
58            false => UIF_A::Clear,
59            true => UIF_A::UpdatePending,
60        }
61    }
62    #[doc = "Checks if the value of the field is `Clear`"]
63    #[inline(always)]
64    pub fn is_clear(&self) -> bool {
65        *self == UIF_A::Clear
66    }
67    #[doc = "Checks if the value of the field is `UpdatePending`"]
68    #[inline(always)]
69    pub fn is_update_pending(&self) -> bool {
70        *self == UIF_A::UpdatePending
71    }
72}
73#[doc = "Field `UIF` writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register."]
74pub type UIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, UIF_A, O>;
75impl<'a, const O: u8> UIF_W<'a, O> {
76    #[doc = "No update occurred"]
77    #[inline(always)]
78    pub fn clear(self) -> &'a mut W {
79        self.variant(UIF_A::Clear)
80    }
81    #[doc = "Update interrupt pending."]
82    #[inline(always)]
83    pub fn update_pending(self) -> &'a mut W {
84        self.variant(UIF_A::UpdatePending)
85    }
86}
87#[doc = "Field `CC1IF` reader - Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)."]
88pub type CC1IF_R = crate::BitReader<bool>;
89#[doc = "Field `CC1IF` writer - Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)."]
90pub type CC1IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
91#[doc = "Field `CC2IF` reader - Capture/Compare 2 interrupt flag Refer to CC1IF description"]
92pub type CC2IF_R = crate::BitReader<bool>;
93#[doc = "Field `CC2IF` writer - Capture/Compare 2 interrupt flag Refer to CC1IF description"]
94pub type CC2IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
95#[doc = "Field `CC3IF` reader - Capture/Compare 3 interrupt flag Refer to CC1IF description"]
96pub type CC3IF_R = crate::BitReader<bool>;
97#[doc = "Field `CC3IF` writer - Capture/Compare 3 interrupt flag Refer to CC1IF description"]
98pub type CC3IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
99#[doc = "Field `CC4IF` reader - Capture/Compare 4 interrupt flag Refer to CC1IF description"]
100pub type CC4IF_R = crate::BitReader<bool>;
101#[doc = "Field `CC4IF` writer - Capture/Compare 4 interrupt flag Refer to CC1IF description"]
102pub type CC4IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
103#[doc = "Field `COMIF` reader - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software."]
104pub type COMIF_R = crate::BitReader<bool>;
105#[doc = "Field `COMIF` writer - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software."]
106pub type COMIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
107#[doc = "Field `TIF` reader - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software."]
108pub type TIF_R = crate::BitReader<bool>;
109#[doc = "Field `TIF` writer - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software."]
110pub type TIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
111#[doc = "Field `BIF` reader - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active."]
112pub type BIF_R = crate::BitReader<bool>;
113#[doc = "Field `BIF` writer - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active."]
114pub type BIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
115#[doc = "Field `B2IF` reader - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active."]
116pub type B2IF_R = crate::BitReader<bool>;
117#[doc = "Field `B2IF` writer - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active."]
118pub type B2IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
119#[doc = "Field `CC1OF` reader - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â\u{80}\u{99}."]
120pub type CC1OF_R = crate::BitReader<bool>;
121#[doc = "Field `CC1OF` writer - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â\u{80}\u{99}."]
122pub type CC1OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
123#[doc = "Field `CC2OF` reader - Capture/Compare 2 overcapture flag Refer to CC1OF description"]
124pub type CC2OF_R = crate::BitReader<bool>;
125#[doc = "Field `CC2OF` writer - Capture/Compare 2 overcapture flag Refer to CC1OF description"]
126pub type CC2OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
127#[doc = "Field `CC3OF` reader - Capture/Compare 3 overcapture flag Refer to CC1OF description"]
128pub type CC3OF_R = crate::BitReader<bool>;
129#[doc = "Field `CC3OF` writer - Capture/Compare 3 overcapture flag Refer to CC1OF description"]
130pub type CC3OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
131#[doc = "Field `CC4OF` reader - Capture/Compare 4 overcapture flag Refer to CC1OF description"]
132pub type CC4OF_R = crate::BitReader<bool>;
133#[doc = "Field `CC4OF` writer - Capture/Compare 4 overcapture flag Refer to CC1OF description"]
134pub type CC4OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
135#[doc = "Field `SBIF` reader - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation."]
136pub type SBIF_R = crate::BitReader<bool>;
137#[doc = "Field `SBIF` writer - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation."]
138pub type SBIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
139#[doc = "Field `CC5IF` reader - Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)"]
140pub type CC5IF_R = crate::BitReader<bool>;
141#[doc = "Field `CC5IF` writer - Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)"]
142pub type CC5IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
143#[doc = "Field `CC6IF` reader - Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)"]
144pub type CC6IF_R = crate::BitReader<bool>;
145#[doc = "Field `CC6IF` writer - Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)"]
146pub type CC6IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
147impl R {
148    #[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register."]
149    #[inline(always)]
150    pub fn uif(&self) -> UIF_R {
151        UIF_R::new((self.bits & 1) != 0)
152    }
153    #[doc = "Bit 1 - Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)."]
154    #[inline(always)]
155    pub fn cc1if(&self) -> CC1IF_R {
156        CC1IF_R::new(((self.bits >> 1) & 1) != 0)
157    }
158    #[doc = "Bit 2 - Capture/Compare 2 interrupt flag Refer to CC1IF description"]
159    #[inline(always)]
160    pub fn cc2if(&self) -> CC2IF_R {
161        CC2IF_R::new(((self.bits >> 2) & 1) != 0)
162    }
163    #[doc = "Bit 3 - Capture/Compare 3 interrupt flag Refer to CC1IF description"]
164    #[inline(always)]
165    pub fn cc3if(&self) -> CC3IF_R {
166        CC3IF_R::new(((self.bits >> 3) & 1) != 0)
167    }
168    #[doc = "Bit 4 - Capture/Compare 4 interrupt flag Refer to CC1IF description"]
169    #[inline(always)]
170    pub fn cc4if(&self) -> CC4IF_R {
171        CC4IF_R::new(((self.bits >> 4) & 1) != 0)
172    }
173    #[doc = "Bit 5 - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software."]
174    #[inline(always)]
175    pub fn comif(&self) -> COMIF_R {
176        COMIF_R::new(((self.bits >> 5) & 1) != 0)
177    }
178    #[doc = "Bit 6 - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software."]
179    #[inline(always)]
180    pub fn tif(&self) -> TIF_R {
181        TIF_R::new(((self.bits >> 6) & 1) != 0)
182    }
183    #[doc = "Bit 7 - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active."]
184    #[inline(always)]
185    pub fn bif(&self) -> BIF_R {
186        BIF_R::new(((self.bits >> 7) & 1) != 0)
187    }
188    #[doc = "Bit 8 - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active."]
189    #[inline(always)]
190    pub fn b2if(&self) -> B2IF_R {
191        B2IF_R::new(((self.bits >> 8) & 1) != 0)
192    }
193    #[doc = "Bit 9 - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â\u{80}\u{99}."]
194    #[inline(always)]
195    pub fn cc1of(&self) -> CC1OF_R {
196        CC1OF_R::new(((self.bits >> 9) & 1) != 0)
197    }
198    #[doc = "Bit 10 - Capture/Compare 2 overcapture flag Refer to CC1OF description"]
199    #[inline(always)]
200    pub fn cc2of(&self) -> CC2OF_R {
201        CC2OF_R::new(((self.bits >> 10) & 1) != 0)
202    }
203    #[doc = "Bit 11 - Capture/Compare 3 overcapture flag Refer to CC1OF description"]
204    #[inline(always)]
205    pub fn cc3of(&self) -> CC3OF_R {
206        CC3OF_R::new(((self.bits >> 11) & 1) != 0)
207    }
208    #[doc = "Bit 12 - Capture/Compare 4 overcapture flag Refer to CC1OF description"]
209    #[inline(always)]
210    pub fn cc4of(&self) -> CC4OF_R {
211        CC4OF_R::new(((self.bits >> 12) & 1) != 0)
212    }
213    #[doc = "Bit 13 - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation."]
214    #[inline(always)]
215    pub fn sbif(&self) -> SBIF_R {
216        SBIF_R::new(((self.bits >> 13) & 1) != 0)
217    }
218    #[doc = "Bit 16 - Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)"]
219    #[inline(always)]
220    pub fn cc5if(&self) -> CC5IF_R {
221        CC5IF_R::new(((self.bits >> 16) & 1) != 0)
222    }
223    #[doc = "Bit 17 - Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)"]
224    #[inline(always)]
225    pub fn cc6if(&self) -> CC6IF_R {
226        CC6IF_R::new(((self.bits >> 17) & 1) != 0)
227    }
228}
229impl W {
230    #[doc = "Bit 0 - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register."]
231    #[inline(always)]
232    pub fn uif(&mut self) -> UIF_W<0> {
233        UIF_W::new(self)
234    }
235    #[doc = "Bit 1 - Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)."]
236    #[inline(always)]
237    pub fn cc1if(&mut self) -> CC1IF_W<1> {
238        CC1IF_W::new(self)
239    }
240    #[doc = "Bit 2 - Capture/Compare 2 interrupt flag Refer to CC1IF description"]
241    #[inline(always)]
242    pub fn cc2if(&mut self) -> CC2IF_W<2> {
243        CC2IF_W::new(self)
244    }
245    #[doc = "Bit 3 - Capture/Compare 3 interrupt flag Refer to CC1IF description"]
246    #[inline(always)]
247    pub fn cc3if(&mut self) -> CC3IF_W<3> {
248        CC3IF_W::new(self)
249    }
250    #[doc = "Bit 4 - Capture/Compare 4 interrupt flag Refer to CC1IF description"]
251    #[inline(always)]
252    pub fn cc4if(&mut self) -> CC4IF_W<4> {
253        CC4IF_W::new(self)
254    }
255    #[doc = "Bit 5 - COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software."]
256    #[inline(always)]
257    pub fn comif(&mut self) -> COMIF_W<5> {
258        COMIF_W::new(self)
259    }
260    #[doc = "Bit 6 - Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software."]
261    #[inline(always)]
262    pub fn tif(&mut self) -> TIF_W<6> {
263        TIF_W::new(self)
264    }
265    #[doc = "Bit 7 - Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active."]
266    #[inline(always)]
267    pub fn bif(&mut self) -> BIF_W<7> {
268        BIF_W::new(self)
269    }
270    #[doc = "Bit 8 - Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active."]
271    #[inline(always)]
272    pub fn b2if(&mut self) -> B2IF_W<8> {
273        B2IF_W::new(self)
274    }
275    #[doc = "Bit 9 - Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â\u{80}\u{99}."]
276    #[inline(always)]
277    pub fn cc1of(&mut self) -> CC1OF_W<9> {
278        CC1OF_W::new(self)
279    }
280    #[doc = "Bit 10 - Capture/Compare 2 overcapture flag Refer to CC1OF description"]
281    #[inline(always)]
282    pub fn cc2of(&mut self) -> CC2OF_W<10> {
283        CC2OF_W::new(self)
284    }
285    #[doc = "Bit 11 - Capture/Compare 3 overcapture flag Refer to CC1OF description"]
286    #[inline(always)]
287    pub fn cc3of(&mut self) -> CC3OF_W<11> {
288        CC3OF_W::new(self)
289    }
290    #[doc = "Bit 12 - Capture/Compare 4 overcapture flag Refer to CC1OF description"]
291    #[inline(always)]
292    pub fn cc4of(&mut self) -> CC4OF_W<12> {
293        CC4OF_W::new(self)
294    }
295    #[doc = "Bit 13 - System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation."]
296    #[inline(always)]
297    pub fn sbif(&mut self) -> SBIF_W<13> {
298        SBIF_W::new(self)
299    }
300    #[doc = "Bit 16 - Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output)"]
301    #[inline(always)]
302    pub fn cc5if(&mut self) -> CC5IF_W<16> {
303        CC5IF_W::new(self)
304    }
305    #[doc = "Bit 17 - Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output)"]
306    #[inline(always)]
307    pub fn cc6if(&mut self) -> CC6IF_W<17> {
308        CC6IF_W::new(self)
309    }
310    #[doc = "Writes raw bits to the register."]
311    #[inline(always)]
312    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
313        self.0.bits(bits);
314        self
315    }
316}
317#[doc = "status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
318pub struct SR_SPEC;
319impl crate::RegisterSpec for SR_SPEC {
320    type Ux = u32;
321}
322#[doc = "`read()` method returns [sr::R](R) reader structure"]
323impl crate::Readable for SR_SPEC {
324    type Reader = R;
325}
326#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"]
327impl crate::Writable for SR_SPEC {
328    type Writer = W;
329}
330#[doc = "`reset()` method sets SR to value 0"]
331impl crate::Resettable for SR_SPEC {
332    #[inline(always)]
333    fn reset_value() -> Self::Ux {
334        0
335    }
336}