stm32g0/stm32g0c1/spi1/
dr.rs

1#[doc = "Register `DR` reader"]
2pub struct R(crate::R<DR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DR` writer"]
17pub struct W(crate::W<DR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DR` reader - Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used."]
38pub type DR_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `DR` writer - Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used."]
40pub type DR_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, DR_SPEC, u16, u16, 16, O>;
41impl R {
42    #[doc = "Bits 0:15 - Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used."]
43    #[inline(always)]
44    pub fn dr(&self) -> DR_R {
45        DR_R::new((self.bits & 0xffff) as u16)
46    }
47}
48impl W {
49    #[doc = "Bits 0:15 - Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used."]
50    #[inline(always)]
51    pub fn dr(&mut self) -> DR_W<0> {
52        DR_W::new(self)
53    }
54    #[doc = "Writes raw bits to the register."]
55    #[inline(always)]
56    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
57        self.0.bits(bits);
58        self
59    }
60}
61#[doc = "SPI data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dr](index.html) module"]
62pub struct DR_SPEC;
63impl crate::RegisterSpec for DR_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [dr::R](R) reader structure"]
67impl crate::Readable for DR_SPEC {
68    type Reader = R;
69}
70#[doc = "`write(|w| ..)` method takes [dr::W](W) writer structure"]
71impl crate::Writable for DR_SPEC {
72    type Writer = W;
73}
74#[doc = "`reset()` method sets DR to value 0"]
75impl crate::Resettable for DR_SPEC {
76    #[inline(always)]
77    fn reset_value() -> Self::Ux {
78        0
79    }
80}
stm32g0/stm32g0c1/spi1/dr.rs

stm32g0/stm32g0c1/spi1/
dr.rs
