stm32g0/stm32g0c1/rtc/
shiftr.rs

1#[doc = "Register `SHIFTR` writer"]
2pub struct W(crate::W<SHIFTR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<SHIFTR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<SHIFTR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<SHIFTR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `SUBFS` writer - Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time."]
23pub type SUBFS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SHIFTR_SPEC, u16, u16, 15, O>;
24#[doc = "Field `ADD1S` writer - Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation."]
25pub type ADD1S_W<'a, const O: u8> = crate::BitWriter<'a, u32, SHIFTR_SPEC, bool, O>;
26impl W {
27    #[doc = "Bits 0:14 - Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time."]
28    #[inline(always)]
29    pub fn subfs(&mut self) -> SUBFS_W<0> {
30        SUBFS_W::new(self)
31    }
32    #[doc = "Bit 31 - Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation."]
33    #[inline(always)]
34    pub fn add1s(&mut self) -> ADD1S_W<31> {
35        ADD1S_W::new(self)
36    }
37    #[doc = "Writes raw bits to the register."]
38    #[inline(always)]
39    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
40        self.0.bits(bits);
41        self
42    }
43}
44#[doc = "RTC shift control register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shiftr](index.html) module"]
45pub struct SHIFTR_SPEC;
46impl crate::RegisterSpec for SHIFTR_SPEC {
47    type Ux = u32;
48}
49#[doc = "`write(|w| ..)` method takes [shiftr::W](W) writer structure"]
50impl crate::Writable for SHIFTR_SPEC {
51    type Writer = W;
52}
53#[doc = "`reset()` method sets SHIFTR to value 0"]
54impl crate::Resettable for SHIFTR_SPEC {
55    #[inline(always)]
56    fn reset_value() -> Self::Ux {
57        0
58    }
59}
stm32g0/stm32g0c1/rtc/shiftr.rs

stm32g0/stm32g0c1/rtc/
shiftr.rs
