stm32g0/stm32g0c1/lptim1/
cr.rs1#[doc = "Register `CR` reader"]
2pub struct R(crate::R<CR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CR` writer"]
17pub struct W(crate::W<CR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ENABLE` reader - LPTIM enable The ENABLE bit is set and cleared by software."]
38pub type ENABLE_R = crate::BitReader<bool>;
39#[doc = "Field `ENABLE` writer - LPTIM enable The ENABLE bit is set and cleared by software."]
40pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
41#[doc = "Field `SNGSTRT` reader - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
42= '00â\u{80}\u{99}), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
43different than '00â\u{80}\u{99}), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware."]
44pub type SNGSTRT_R = crate::BitReader<bool>;
45#[doc = "Field `SNGSTRT` writer - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
46= '00â\u{80}\u{99}), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
47different than '00â\u{80}\u{99}), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware."]
48pub type SNGSTRT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
49#[doc = "Field `CNTSTRT` reader - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
50= '00â\u{80}\u{99}), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
51different than '00â\u{80}\u{99}), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware."]
52pub type CNTSTRT_R = crate::BitReader<bool>;
53#[doc = "Field `CNTSTRT` writer - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
54= '00â\u{80}\u{99}), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
55different than '00â\u{80}\u{99}), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware."]
56pub type CNTSTRT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
57#[doc = "Field `COUNTRST` reader - Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'."]
58pub type COUNTRST_R = crate::BitReader<bool>;
59#[doc = "Field `COUNTRST` writer - Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'."]
60pub type COUNTRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
61#[doc = "Field `RSTARE` reader - Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content."]
62pub type RSTARE_R = crate::BitReader<bool>;
63#[doc = "Field `RSTARE` writer - Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content."]
64pub type RSTARE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
65impl R {
66 #[doc = "Bit 0 - LPTIM enable The ENABLE bit is set and cleared by software."]
67 #[inline(always)]
68 pub fn enable(&self) -> ENABLE_R {
69 ENABLE_R::new((self.bits & 1) != 0)
70 }
71 #[doc = "Bit 1 - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
72= '00â\u{80}\u{99}), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
73different than '00â\u{80}\u{99}), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware."]
74 #[inline(always)]
75 pub fn sngstrt(&self) -> SNGSTRT_R {
76 SNGSTRT_R::new(((self.bits >> 1) & 1) != 0)
77 }
78 #[doc = "Bit 2 - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
79= '00â\u{80}\u{99}), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
80different than '00â\u{80}\u{99}), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware."]
81 #[inline(always)]
82 pub fn cntstrt(&self) -> CNTSTRT_R {
83 CNTSTRT_R::new(((self.bits >> 2) & 1) != 0)
84 }
85 #[doc = "Bit 3 - Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'."]
86 #[inline(always)]
87 pub fn countrst(&self) -> COUNTRST_R {
88 COUNTRST_R::new(((self.bits >> 3) & 1) != 0)
89 }
90 #[doc = "Bit 4 - Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content."]
91 #[inline(always)]
92 pub fn rstare(&self) -> RSTARE_R {
93 RSTARE_R::new(((self.bits >> 4) & 1) != 0)
94 }
95}
96impl W {
97 #[doc = "Bit 0 - LPTIM enable The ENABLE bit is set and cleared by software."]
98 #[inline(always)]
99 pub fn enable(&mut self) -> ENABLE_W<0> {
100 ENABLE_W::new(self)
101 }
102 #[doc = "Bit 1 - LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
103= '00â\u{80}\u{99}), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN\\[1:0\\]
104different than '00â\u{80}\u{99}), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware."]
105 #[inline(always)]
106 pub fn sngstrt(&mut self) -> SNGSTRT_W<1> {
107 SNGSTRT_W::new(self)
108 }
109 #[doc = "Bit 2 - Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN\\[1:0\\]
110= '00â\u{80}\u{99}), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN\\[1:0\\]
111different than '00â\u{80}\u{99}), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware."]
112 #[inline(always)]
113 pub fn cntstrt(&mut self) -> CNTSTRT_W<2> {
114 CNTSTRT_W::new(self)
115 }
116 #[doc = "Bit 3 - Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'."]
117 #[inline(always)]
118 pub fn countrst(&mut self) -> COUNTRST_W<3> {
119 COUNTRST_W::new(self)
120 }
121 #[doc = "Bit 4 - Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register will asynchronously reset LPTIM_CNT register content."]
122 #[inline(always)]
123 pub fn rstare(&mut self) -> RSTARE_W<4> {
124 RSTARE_W::new(self)
125 }
126 #[doc = "Writes raw bits to the register."]
127 #[inline(always)]
128 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
129 self.0.bits(bits);
130 self
131 }
132}
133#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
134pub struct CR_SPEC;
135impl crate::RegisterSpec for CR_SPEC {
136 type Ux = u32;
137}
138#[doc = "`read()` method returns [cr::R](R) reader structure"]
139impl crate::Readable for CR_SPEC {
140 type Reader = R;
141}
142#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
143impl crate::Writable for CR_SPEC {
144 type Writer = W;
145}
146#[doc = "`reset()` method sets CR to value 0"]
147impl crate::Resettable for CR_SPEC {
148 #[inline(always)]
149 fn reset_value() -> Self::Ux {
150 0
151 }
152}