stm32g0/stm32g0b0/gpioa/
odr.rs

1#[doc = "Register `ODR` reader"]
2pub struct R(crate::R<ODR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ODR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ODR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ODR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ODR` writer"]
17pub struct W(crate::W<ODR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ODR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ODR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ODR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Port output data (y = 0..15)"]
38pub use ODR0_A as ODR15_A;
39#[doc = "Port output data (y = 0..15)"]
40pub use ODR0_A as ODR14_A;
41#[doc = "Port output data (y = 0..15)"]
42pub use ODR0_A as ODR13_A;
43#[doc = "Port output data (y = 0..15)"]
44pub use ODR0_A as ODR12_A;
45#[doc = "Port output data (y = 0..15)"]
46pub use ODR0_A as ODR11_A;
47#[doc = "Port output data (y = 0..15)"]
48pub use ODR0_A as ODR10_A;
49#[doc = "Port output data (y = 0..15)"]
50pub use ODR0_A as ODR9_A;
51#[doc = "Port output data (y = 0..15)"]
52pub use ODR0_A as ODR8_A;
53#[doc = "Port output data (y = 0..15)"]
54pub use ODR0_A as ODR7_A;
55#[doc = "Port output data (y = 0..15)"]
56pub use ODR0_A as ODR6_A;
57#[doc = "Port output data (y = 0..15)"]
58pub use ODR0_A as ODR5_A;
59#[doc = "Port output data (y = 0..15)"]
60pub use ODR0_A as ODR4_A;
61#[doc = "Port output data (y = 0..15)"]
62pub use ODR0_A as ODR3_A;
63#[doc = "Port output data (y = 0..15)"]
64pub use ODR0_A as ODR2_A;
65#[doc = "Port output data (y = 0..15)"]
66pub use ODR0_A as ODR1_A;
67#[doc = "Field `ODR15` reader - Port output data (y = 0..15)"]
68pub use ODR0_R as ODR15_R;
69#[doc = "Field `ODR14` reader - Port output data (y = 0..15)"]
70pub use ODR0_R as ODR14_R;
71#[doc = "Field `ODR13` reader - Port output data (y = 0..15)"]
72pub use ODR0_R as ODR13_R;
73#[doc = "Field `ODR12` reader - Port output data (y = 0..15)"]
74pub use ODR0_R as ODR12_R;
75#[doc = "Field `ODR11` reader - Port output data (y = 0..15)"]
76pub use ODR0_R as ODR11_R;
77#[doc = "Field `ODR10` reader - Port output data (y = 0..15)"]
78pub use ODR0_R as ODR10_R;
79#[doc = "Field `ODR9` reader - Port output data (y = 0..15)"]
80pub use ODR0_R as ODR9_R;
81#[doc = "Field `ODR8` reader - Port output data (y = 0..15)"]
82pub use ODR0_R as ODR8_R;
83#[doc = "Field `ODR7` reader - Port output data (y = 0..15)"]
84pub use ODR0_R as ODR7_R;
85#[doc = "Field `ODR6` reader - Port output data (y = 0..15)"]
86pub use ODR0_R as ODR6_R;
87#[doc = "Field `ODR5` reader - Port output data (y = 0..15)"]
88pub use ODR0_R as ODR5_R;
89#[doc = "Field `ODR4` reader - Port output data (y = 0..15)"]
90pub use ODR0_R as ODR4_R;
91#[doc = "Field `ODR3` reader - Port output data (y = 0..15)"]
92pub use ODR0_R as ODR3_R;
93#[doc = "Field `ODR2` reader - Port output data (y = 0..15)"]
94pub use ODR0_R as ODR2_R;
95#[doc = "Field `ODR1` reader - Port output data (y = 0..15)"]
96pub use ODR0_R as ODR1_R;
97#[doc = "Field `ODR15` writer - Port output data (y = 0..15)"]
98pub use ODR0_W as ODR15_W;
99#[doc = "Field `ODR14` writer - Port output data (y = 0..15)"]
100pub use ODR0_W as ODR14_W;
101#[doc = "Field `ODR13` writer - Port output data (y = 0..15)"]
102pub use ODR0_W as ODR13_W;
103#[doc = "Field `ODR12` writer - Port output data (y = 0..15)"]
104pub use ODR0_W as ODR12_W;
105#[doc = "Field `ODR11` writer - Port output data (y = 0..15)"]
106pub use ODR0_W as ODR11_W;
107#[doc = "Field `ODR10` writer - Port output data (y = 0..15)"]
108pub use ODR0_W as ODR10_W;
109#[doc = "Field `ODR9` writer - Port output data (y = 0..15)"]
110pub use ODR0_W as ODR9_W;
111#[doc = "Field `ODR8` writer - Port output data (y = 0..15)"]
112pub use ODR0_W as ODR8_W;
113#[doc = "Field `ODR7` writer - Port output data (y = 0..15)"]
114pub use ODR0_W as ODR7_W;
115#[doc = "Field `ODR6` writer - Port output data (y = 0..15)"]
116pub use ODR0_W as ODR6_W;
117#[doc = "Field `ODR5` writer - Port output data (y = 0..15)"]
118pub use ODR0_W as ODR5_W;
119#[doc = "Field `ODR4` writer - Port output data (y = 0..15)"]
120pub use ODR0_W as ODR4_W;
121#[doc = "Field `ODR3` writer - Port output data (y = 0..15)"]
122pub use ODR0_W as ODR3_W;
123#[doc = "Field `ODR2` writer - Port output data (y = 0..15)"]
124pub use ODR0_W as ODR2_W;
125#[doc = "Field `ODR1` writer - Port output data (y = 0..15)"]
126pub use ODR0_W as ODR1_W;
127#[doc = "Port output data (y = 0..15)\n\nValue on reset: 0"]
128#[derive(Clone, Copy, Debug, PartialEq)]
129pub enum ODR0_A {
130    #[doc = "0: Set output to logic low"]
131    Low = 0,
132    #[doc = "1: Set output to logic high"]
133    High = 1,
134}
135impl From<ODR0_A> for bool {
136    #[inline(always)]
137    fn from(variant: ODR0_A) -> Self {
138        variant as u8 != 0
139    }
140}
141#[doc = "Field `ODR0` reader - Port output data (y = 0..15)"]
142pub type ODR0_R = crate::BitReader<ODR0_A>;
143impl ODR0_R {
144    #[doc = "Get enumerated values variant"]
145    #[inline(always)]
146    pub fn variant(&self) -> ODR0_A {
147        match self.bits {
148            false => ODR0_A::Low,
149            true => ODR0_A::High,
150        }
151    }
152    #[doc = "Checks if the value of the field is `Low`"]
153    #[inline(always)]
154    pub fn is_low(&self) -> bool {
155        *self == ODR0_A::Low
156    }
157    #[doc = "Checks if the value of the field is `High`"]
158    #[inline(always)]
159    pub fn is_high(&self) -> bool {
160        *self == ODR0_A::High
161    }
162}
163#[doc = "Field `ODR0` writer - Port output data (y = 0..15)"]
164pub type ODR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, ODR_SPEC, ODR0_A, O>;
165impl<'a, const O: u8> ODR0_W<'a, O> {
166    #[doc = "Set output to logic low"]
167    #[inline(always)]
168    pub fn low(self) -> &'a mut W {
169        self.variant(ODR0_A::Low)
170    }
171    #[doc = "Set output to logic high"]
172    #[inline(always)]
173    pub fn high(self) -> &'a mut W {
174        self.variant(ODR0_A::High)
175    }
176}
177impl R {
178    #[doc = "Bit 15 - Port output data (y = 0..15)"]
179    #[inline(always)]
180    pub fn odr15(&self) -> ODR15_R {
181        ODR15_R::new(((self.bits >> 15) & 1) != 0)
182    }
183    #[doc = "Bit 14 - Port output data (y = 0..15)"]
184    #[inline(always)]
185    pub fn odr14(&self) -> ODR14_R {
186        ODR14_R::new(((self.bits >> 14) & 1) != 0)
187    }
188    #[doc = "Bit 13 - Port output data (y = 0..15)"]
189    #[inline(always)]
190    pub fn odr13(&self) -> ODR13_R {
191        ODR13_R::new(((self.bits >> 13) & 1) != 0)
192    }
193    #[doc = "Bit 12 - Port output data (y = 0..15)"]
194    #[inline(always)]
195    pub fn odr12(&self) -> ODR12_R {
196        ODR12_R::new(((self.bits >> 12) & 1) != 0)
197    }
198    #[doc = "Bit 11 - Port output data (y = 0..15)"]
199    #[inline(always)]
200    pub fn odr11(&self) -> ODR11_R {
201        ODR11_R::new(((self.bits >> 11) & 1) != 0)
202    }
203    #[doc = "Bit 10 - Port output data (y = 0..15)"]
204    #[inline(always)]
205    pub fn odr10(&self) -> ODR10_R {
206        ODR10_R::new(((self.bits >> 10) & 1) != 0)
207    }
208    #[doc = "Bit 9 - Port output data (y = 0..15)"]
209    #[inline(always)]
210    pub fn odr9(&self) -> ODR9_R {
211        ODR9_R::new(((self.bits >> 9) & 1) != 0)
212    }
213    #[doc = "Bit 8 - Port output data (y = 0..15)"]
214    #[inline(always)]
215    pub fn odr8(&self) -> ODR8_R {
216        ODR8_R::new(((self.bits >> 8) & 1) != 0)
217    }
218    #[doc = "Bit 7 - Port output data (y = 0..15)"]
219    #[inline(always)]
220    pub fn odr7(&self) -> ODR7_R {
221        ODR7_R::new(((self.bits >> 7) & 1) != 0)
222    }
223    #[doc = "Bit 6 - Port output data (y = 0..15)"]
224    #[inline(always)]
225    pub fn odr6(&self) -> ODR6_R {
226        ODR6_R::new(((self.bits >> 6) & 1) != 0)
227    }
228    #[doc = "Bit 5 - Port output data (y = 0..15)"]
229    #[inline(always)]
230    pub fn odr5(&self) -> ODR5_R {
231        ODR5_R::new(((self.bits >> 5) & 1) != 0)
232    }
233    #[doc = "Bit 4 - Port output data (y = 0..15)"]
234    #[inline(always)]
235    pub fn odr4(&self) -> ODR4_R {
236        ODR4_R::new(((self.bits >> 4) & 1) != 0)
237    }
238    #[doc = "Bit 3 - Port output data (y = 0..15)"]
239    #[inline(always)]
240    pub fn odr3(&self) -> ODR3_R {
241        ODR3_R::new(((self.bits >> 3) & 1) != 0)
242    }
243    #[doc = "Bit 2 - Port output data (y = 0..15)"]
244    #[inline(always)]
245    pub fn odr2(&self) -> ODR2_R {
246        ODR2_R::new(((self.bits >> 2) & 1) != 0)
247    }
248    #[doc = "Bit 1 - Port output data (y = 0..15)"]
249    #[inline(always)]
250    pub fn odr1(&self) -> ODR1_R {
251        ODR1_R::new(((self.bits >> 1) & 1) != 0)
252    }
253    #[doc = "Bit 0 - Port output data (y = 0..15)"]
254    #[inline(always)]
255    pub fn odr0(&self) -> ODR0_R {
256        ODR0_R::new((self.bits & 1) != 0)
257    }
258}
259impl W {
260    #[doc = "Bit 15 - Port output data (y = 0..15)"]
261    #[inline(always)]
262    pub fn odr15(&mut self) -> ODR15_W<15> {
263        ODR15_W::new(self)
264    }
265    #[doc = "Bit 14 - Port output data (y = 0..15)"]
266    #[inline(always)]
267    pub fn odr14(&mut self) -> ODR14_W<14> {
268        ODR14_W::new(self)
269    }
270    #[doc = "Bit 13 - Port output data (y = 0..15)"]
271    #[inline(always)]
272    pub fn odr13(&mut self) -> ODR13_W<13> {
273        ODR13_W::new(self)
274    }
275    #[doc = "Bit 12 - Port output data (y = 0..15)"]
276    #[inline(always)]
277    pub fn odr12(&mut self) -> ODR12_W<12> {
278        ODR12_W::new(self)
279    }
280    #[doc = "Bit 11 - Port output data (y = 0..15)"]
281    #[inline(always)]
282    pub fn odr11(&mut self) -> ODR11_W<11> {
283        ODR11_W::new(self)
284    }
285    #[doc = "Bit 10 - Port output data (y = 0..15)"]
286    #[inline(always)]
287    pub fn odr10(&mut self) -> ODR10_W<10> {
288        ODR10_W::new(self)
289    }
290    #[doc = "Bit 9 - Port output data (y = 0..15)"]
291    #[inline(always)]
292    pub fn odr9(&mut self) -> ODR9_W<9> {
293        ODR9_W::new(self)
294    }
295    #[doc = "Bit 8 - Port output data (y = 0..15)"]
296    #[inline(always)]
297    pub fn odr8(&mut self) -> ODR8_W<8> {
298        ODR8_W::new(self)
299    }
300    #[doc = "Bit 7 - Port output data (y = 0..15)"]
301    #[inline(always)]
302    pub fn odr7(&mut self) -> ODR7_W<7> {
303        ODR7_W::new(self)
304    }
305    #[doc = "Bit 6 - Port output data (y = 0..15)"]
306    #[inline(always)]
307    pub fn odr6(&mut self) -> ODR6_W<6> {
308        ODR6_W::new(self)
309    }
310    #[doc = "Bit 5 - Port output data (y = 0..15)"]
311    #[inline(always)]
312    pub fn odr5(&mut self) -> ODR5_W<5> {
313        ODR5_W::new(self)
314    }
315    #[doc = "Bit 4 - Port output data (y = 0..15)"]
316    #[inline(always)]
317    pub fn odr4(&mut self) -> ODR4_W<4> {
318        ODR4_W::new(self)
319    }
320    #[doc = "Bit 3 - Port output data (y = 0..15)"]
321    #[inline(always)]
322    pub fn odr3(&mut self) -> ODR3_W<3> {
323        ODR3_W::new(self)
324    }
325    #[doc = "Bit 2 - Port output data (y = 0..15)"]
326    #[inline(always)]
327    pub fn odr2(&mut self) -> ODR2_W<2> {
328        ODR2_W::new(self)
329    }
330    #[doc = "Bit 1 - Port output data (y = 0..15)"]
331    #[inline(always)]
332    pub fn odr1(&mut self) -> ODR1_W<1> {
333        ODR1_W::new(self)
334    }
335    #[doc = "Bit 0 - Port output data (y = 0..15)"]
336    #[inline(always)]
337    pub fn odr0(&mut self) -> ODR0_W<0> {
338        ODR0_W::new(self)
339    }
340    #[doc = "Writes raw bits to the register."]
341    #[inline(always)]
342    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
343        self.0.bits(bits);
344        self
345    }
346}
347#[doc = "GPIO port output data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [odr](index.html) module"]
348pub struct ODR_SPEC;
349impl crate::RegisterSpec for ODR_SPEC {
350    type Ux = u32;
351}
352#[doc = "`read()` method returns [odr::R](R) reader structure"]
353impl crate::Readable for ODR_SPEC {
354    type Reader = R;
355}
356#[doc = "`write(|w| ..)` method takes [odr::W](W) writer structure"]
357impl crate::Writable for ODR_SPEC {
358    type Writer = W;
359}
360#[doc = "`reset()` method sets ODR to value 0"]
361impl crate::Resettable for ODR_SPEC {
362    #[inline(always)]
363    fn reset_value() -> Self::Ux {
364        0
365    }
366}
stm32g0/stm32g0b0/gpioa/odr.rs

stm32g0/stm32g0b0/gpioa/
odr.rs
