stm32g0/stm32g081/rtc/
icsr.rs

1#[doc = "Register `ICSR` reader"]
2pub struct R(crate::R<ICSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ICSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ICSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ICSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ICSR` writer"]
17pub struct W(crate::W<ICSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ICSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ICSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ICSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ALRAWF` reader - Alarm A write flag"]
38pub type ALRAWF_R = crate::BitReader<bool>;
39#[doc = "Field `ALRBWF` reader - Alarm B write flag"]
40pub type ALRBWF_R = crate::BitReader<bool>;
41#[doc = "Field `WUTWF` reader - Wakeup timer write flag"]
42pub type WUTWF_R = crate::BitReader<bool>;
43#[doc = "Field `SHPF` reader - Shift operation pending"]
44pub type SHPF_R = crate::BitReader<bool>;
45#[doc = "Field `SHPF` writer - Shift operation pending"]
46pub type SHPF_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICSR_SPEC, bool, O>;
47#[doc = "Field `INITS` reader - Initialization status flag"]
48pub type INITS_R = crate::BitReader<bool>;
49#[doc = "Field `RSF` reader - Registers synchronization flag"]
50pub type RSF_R = crate::BitReader<bool>;
51#[doc = "Field `RSF` writer - Registers synchronization flag"]
52pub type RSF_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICSR_SPEC, bool, O>;
53#[doc = "Field `INITF` reader - Initialization flag"]
54pub type INITF_R = crate::BitReader<bool>;
55#[doc = "Field `INIT` reader - Initialization mode"]
56pub type INIT_R = crate::BitReader<bool>;
57#[doc = "Field `INIT` writer - Initialization mode"]
58pub type INIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICSR_SPEC, bool, O>;
59#[doc = "Field `RECALPF` reader - Recalibration pending Flag"]
60pub type RECALPF_R = crate::BitReader<bool>;
61impl R {
62    #[doc = "Bit 0 - Alarm A write flag"]
63    #[inline(always)]
64    pub fn alrawf(&self) -> ALRAWF_R {
65        ALRAWF_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bit 1 - Alarm B write flag"]
68    #[inline(always)]
69    pub fn alrbwf(&self) -> ALRBWF_R {
70        ALRBWF_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    #[doc = "Bit 2 - Wakeup timer write flag"]
73    #[inline(always)]
74    pub fn wutwf(&self) -> WUTWF_R {
75        WUTWF_R::new(((self.bits >> 2) & 1) != 0)
76    }
77    #[doc = "Bit 3 - Shift operation pending"]
78    #[inline(always)]
79    pub fn shpf(&self) -> SHPF_R {
80        SHPF_R::new(((self.bits >> 3) & 1) != 0)
81    }
82    #[doc = "Bit 4 - Initialization status flag"]
83    #[inline(always)]
84    pub fn inits(&self) -> INITS_R {
85        INITS_R::new(((self.bits >> 4) & 1) != 0)
86    }
87    #[doc = "Bit 5 - Registers synchronization flag"]
88    #[inline(always)]
89    pub fn rsf(&self) -> RSF_R {
90        RSF_R::new(((self.bits >> 5) & 1) != 0)
91    }
92    #[doc = "Bit 6 - Initialization flag"]
93    #[inline(always)]
94    pub fn initf(&self) -> INITF_R {
95        INITF_R::new(((self.bits >> 6) & 1) != 0)
96    }
97    #[doc = "Bit 7 - Initialization mode"]
98    #[inline(always)]
99    pub fn init(&self) -> INIT_R {
100        INIT_R::new(((self.bits >> 7) & 1) != 0)
101    }
102    #[doc = "Bit 16 - Recalibration pending Flag"]
103    #[inline(always)]
104    pub fn recalpf(&self) -> RECALPF_R {
105        RECALPF_R::new(((self.bits >> 16) & 1) != 0)
106    }
107}
108impl W {
109    #[doc = "Bit 3 - Shift operation pending"]
110    #[inline(always)]
111    pub fn shpf(&mut self) -> SHPF_W<3> {
112        SHPF_W::new(self)
113    }
114    #[doc = "Bit 5 - Registers synchronization flag"]
115    #[inline(always)]
116    pub fn rsf(&mut self) -> RSF_W<5> {
117        RSF_W::new(self)
118    }
119    #[doc = "Bit 7 - Initialization mode"]
120    #[inline(always)]
121    pub fn init(&mut self) -> INIT_W<7> {
122        INIT_W::new(self)
123    }
124    #[doc = "Writes raw bits to the register."]
125    #[inline(always)]
126    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127        self.0.bits(bits);
128        self
129    }
130}
131#[doc = "initialization and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icsr](index.html) module"]
132pub struct ICSR_SPEC;
133impl crate::RegisterSpec for ICSR_SPEC {
134    type Ux = u32;
135}
136#[doc = "`read()` method returns [icsr::R](R) reader structure"]
137impl crate::Readable for ICSR_SPEC {
138    type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [icsr::W](W) writer structure"]
141impl crate::Writable for ICSR_SPEC {
142    type Writer = W;
143}
144#[doc = "`reset()` method sets ICSR to value 0x07"]
145impl crate::Resettable for ICSR_SPEC {
146    #[inline(always)]
147    fn reset_value() -> Self::Ux {
148        0x07
149    }
150}
stm32g0/stm32g081/rtc/icsr.rs

stm32g0/stm32g081/rtc/
icsr.rs
