Struct stm32g0::stm32g0c1::usart1::cr2::LBCL_W

pub struct LBCL_W<'a> { /* fields omitted */ }

Field LBCL writer - Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

Implementations

impl<'a> LBCL_W<'a>

pub fn variant(self, variant: LBCL_A) -> &'a mut W

Writes variant to the field

pub fn b_0x0(self) -> &'a mut W

The clock pulse of the last data bit is not output to the SCLK pin

pub fn b_0x1(self) -> &'a mut W

The clock pulse of the last data bit is output to the SCLK pin

pub fn set_bit(self) -> &'a mut W

Sets the field bit

pub fn clear_bit(self) -> &'a mut W

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W

Writes raw bits to the field